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8A34046 PDF预览

8A34046

更新时间: 2024-09-25 14:58:11
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
100页 2247K
描述
SETS for SyncE and OTN

8A34046 数据手册

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8A34046  
Datasheet  
SETS for SyncE and OTN  
12 differential / 24 LVCMOS outputs  
Overview  
Frequencies from 0.5Hz to 1GHz (250MHz for LVCMOS)  
Jitter below 150fs RMS (10kHz to 20MHz)  
Supports LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL,  
and HSTL output modes  
The 8A34046 Synchronous Equipment Timing Source (SETS) for  
Synchronous Ethernet (SyncE) and Optical Transport Network  
(OTN) is a highly integrated timing device with four Digital PLL  
(DPLL) channels and four Digitally Controlled Oscillator (DCO)  
channels. The DPLLs can lock to external references or operate in  
free run, and can be configured as DCOs. Each of the DCOs can  
be synchronized by any of the DPLLs or they can operate in free  
run. The DCOs can alternatively be controlled by an external  
algorithm for Optical Transport Network (OTN) applications.  
Differential output swing is selectable: 400mV / 650mV /  
800mV / 910mV  
Independent output voltages of 3.3V, 2.5V, or 1.8V  
LVCMOS additionally supports 1.5V or 1.2V  
The clock phase of each output is individually programmable  
in 1ns to 2ns steps with a total range of ±180°  
Typical Applications  
4 differential / 8 single-ended clock inputs  
Core and access IP switches / routers  
Supports frequencies from 1kHz to 1GHz  
Any input can be mapped to any or all of the timing channels  
Redundant inputs frequency independent of each other  
Any input can be designated as external frame/sync pulse of  
PPES (pulse per even second), 1PPS (Pulse per Second),  
5PPS, 10PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8kHz  
associated with a selectable reference clock input  
Synchronous Ethernet equipment  
10Gb, 40Gb, and 100Gb Ethernet interfaces  
Wireless infrastructure for 4.5G and 5G network equipment  
OTN muxponders and line cards  
Features  
Compliant with G.8262 option 1 and option 2, and G.8262.1  
Supports ITU-T G.709 frequencies  
Meets OTN jitter and wander requirements per ITU-T G.8251  
Four independent DPLL/DCO channels  
Per-input programmable phase offset of up to ±1.638s in  
50ps steps  
Reference monitors qualify/disqualify references depending on  
LOS, activity, frequency monitoring, and/or LOS input pins  
Loss of Signal (LOS) input pins (via GPIOs) can be assigned  
to any input clock reference  
Each can act as a frequency synthesizer, jitter attenuator,  
Digitally Controlled Oscillator (DCO), or Digital Phase Lock  
Loop (DPLL)  
Automatic reference selection state machines select the active  
reference for each DPLL based on the reference monitors,  
priority tables, revertive / non-revertive, and other  
programmable settings  
DPLL Digital Loop Filters (DLFs) are programmable with  
cut-off frequencies from 0.1Hz to 22kHz  
Each DPLL generates an output frequency via a Fractional  
Output Divider (FOD)  
System APLL operates from fundamental-mode crystal: 25MHz  
to 54MHz or from a crystal oscillator  
Each FOD supports output phase tuning with 50ps  
resolution  
System DPLL accepts an XO, TCXO, or OCXO operating at  
virtually any frequency from 1MHz to 150MHz  
Four independent DCO channels  
DPLLs can be configured as DCOs to synthesize clocks under  
the control of an external algorithm  
Each DCO generates an independent output frequency via a  
Fractional Output Divider (FOD)  
DCOs generate with frequency resolution less than  
1.11 × 10-16  
DPLL/DCO and DCO channels can be configured as Satellite  
Channels that increase the number of independently  
programmable FODs and output stages available to other  
DPLL/DCO or DCO channels  
Supports 1MHz I2C or 50MHz SPI serial processor ports  
Can configure itself automatically after reset via:  
Internal customer definable One-Time Programmable (OTP)  
memory with up to 16 different configurations  
Standard external I2C EEPROM if serial port in I2C mode  
1149.1 JTAG Boundary Scan  
10 × 10 mm 72-VFQFPN package  
©2022 Renesas Electronics Corporation  
1
February 22, 2022  

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