Datasheet > 8A34012

8A34012

更新时间： 2024-09-26 14:57:23

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
103页	2274K
描述
Line Card Synchronizer for IEEE 1588 - Four Channels

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

8A34012 数据手册

Port Synchronizer for IEEE 1588

Frequency and Time/Phase

8A34012

Datasheet

▪ 7 differential / 14 single-ended clock inputs

• Support frequencies from 1kHz to 1GHz

Overview

The 8A34012 is a port synchronizer for frequency and time/phase

for equipment that uses packet-based and physical layer-based

equipment synchronization.

• Any input can be mapped to any or all of the timing channels

• Redundant inputs frequency independent of each other

• Any input can be designated as external frame/sync pulse of

PPES (pulse per even second), 1 PPS (Pulse per Second),

5PPS, 10 PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8kHz

associated with a selectable reference clock input

The 8A34012 is a highly integrated device that provides tools to

manage timing references, clock sources, and timing paths for

IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The

PLL channels can act independently as frequency synthesizers,

jitter attenuators, Digitally Controlled Oscillators (DCO) or Digital

Phase Lock Loops (DPLL).

• Per-input programmable phase offset of up to ±1.638s in

1ps steps

▪ Reference monitors qualify/disqualify references depending on

LOS, activity, frequency monitoring and/or LOS input pins

Typical Applications

• Loss of Signal (LOS) input pins (via GPIOs) can be assigned

to any input clock reference

▪ Core and access IP switches / routers

▪ Synchronous Ethernet equipment

▪ Automatic reference selection state machines select the active

reference for each DPLL based on the reference monitors,

priority tables, revertive / non-revertive, and other

programmable settings

▪ Telecom Boundary Clocks (T-BCs) and Telecom Time Slave

Clocks (T-TSCs) according to ITU-T G.8273.2

▪ 10Gb, 40Gb and 100Gb Ethernet interfaces

▪ System APLL operates from fundamental-mode crystal: 25MHz

to 54MHz or from a crystal oscillator

▪ Central Office Timing Source and Distribution

▪ Wireless infrastructure for 4.5G and 5G network equipment

▪ System DPLL accepts an XO, TCXO, or OCXO operating at

virtually any frequency from 1MHz to 150MHz

Features

▪ Four independent timing channels

▪ DPLLs can be configured as DCOs to synthesize Precision

Time Protocol (PTP) / IEEE 1588 clocks

• Each can act as a frequency synthesizer, jitter attenuator,

Digitally Controlled Oscillator (DCO), or Digital Phase Lock

Loop (DPLL)

• DCOs generate PTP based clocks with frequency resolution

less than 1.11 × 10^-16

▪ DPLL Phase detectors can be used as Time-to-Digital

Converters (TDC) with precision below 1ps

▪ Supports 1MHz I²C or 50MHz SPI serial processor ports

• DPLL Digital Loop Filters (DLFs) are programmable with

cut-off frequencies from 17Hz to 22kHz

• Switching between DPLL and DCO modes is hitless and

dynamic

▪ Can configure itself automatically after reset via:

• Internal customer definable One-Time Programmable

memory with up to 16 different configurations

• Standard external I²C EPROM via separate I²C Master Port

• Generates output frequencies that are independent of input

frequencies via a Fractional Output Divider (FOD)

• Each FOD supports output phase tuning with 1ps resolution

▪ 8 Differential / 16 LVCMOS outputs

▪ 1149.1 JTAG Boundary Scan

▪ 10 × 10 mm, 72-QFN package

• Frequencies from 0.5Hz to 1GHz (250MHz for LVCMOS)

• Jitter below 150fs RMS (10kHz to 20MHz)

• LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL, and HSTL

output modes supported

• Differential output swing is selectable: 400mV / 650mV /

800mV / 910mV

• Independent output voltages of 3.3V, 2.5V, or 1.8V

▪ LVCMOS additionally supports 1.5V or 1.2V

• The clock phase of each output is individually programmable

in 1ns to 2ns steps with a total range of ±180°

November 30, 2021

12 3 4 5 6 7...103

中文翻译

下载PDF

与8A34012相关器件

型号	品牌	获取价格	描述	数据表
8A34013	RENESAS	获取价格	Line Card Synchronizer for IEEE 1588 - Four Channels
8A34041	RENESAS	获取价格	Multichannel DPLL / DCO - Eight Channels
8A34042	RENESAS	获取价格	Multichannel DPLL / DCO - Four Channels
8A34043	RENESAS	获取价格	Multichannel DPLL / DCO - Four Channels
8A34044	RENESAS	获取价格	Multichannel DPLL / DCO - Four / Eight Channels
8A34045	RENESAS	获取价格	Multichannel DPLL / DCO - Two / Eight Channels
8A34046	RENESAS	获取价格	SETS for SyncE and OTN
8A36-01-1-02S-F	GRAYHILL	获取价格	Rotary Switch, 2 Positions, SPDT, Maintained, 0.25A, 28VDC, Solder Lug Terminal, Rotary Sh
8A36-01-1-10S-F	GRAYHILL	获取价格	Rotary Switch, 10 Positions, SP10T, Maintained, 0.25A, 28VDC, Solder Lug Terminal, Rotary
8A36-03-1-02N-F	GRAYHILL	获取价格	Rotary Switch, 2 Positions, 3PDT, Maintained, 0.25A, 28VDC, Solder Lug Terminal, Rotary Sh

与8A34012相关文章

SK海力士量产12层HBM3E，容量高达36GB
2024-09-27

11
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
2024-09-27

14
摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

81
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

72

产品中心

服务支持

精选活动

关于我们

帮助中心

8A34012

8A34012 数据手册

与8A34012相关器件

与8A34012相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

8A34012

8A34012 数据手册

与8A34012相关器件

与8A34012相关文章

您还可以找

您在本页遇到什么问题？