8A34005
Datasheet
Synchronization Management Unit
▪ 12 Differential / 24 LVCMOS outputs
Overview
• Frequencies from 0.5Hz to 1GHz (250MHz for LVCMOS)
• Jitter below 150fs RMS (10kHz to 20MHz)
The 8A34005 Synchronization Management Unit (SMU) provides
tools to manage timing references, clock sources, and timing
paths for IEEE 1588 and Synchronous Ethernet (SyncE) based
clocks. The PLL channels can act independently as frequency
synthesizers, jitter attenuators, Digitally Controlled Oscillators
(DCO), or Digital Phase Lock Loops (DPLL).
• LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL, and HSTL
output modes supported
• Differential output swing is selectable: 400mV / 650mV /
800mV / 910mV
• Independent output voltages of 3.3V, 2.5V, or 1.8V
• LVCMOS additionally supports 1.5V or 1.2V
Optional IEEE 1588 software is available under license from
Renesas for use with the 8A34005. The software includes clock
recovery servos that can be used with the Linux PTP IEEE 1588
protocol stack or with other IEEE 1588 protocol stacks.
• The clock phase of each output is individually programmable
in 1ns to 2ns steps with a total range of ±180°
▪ 2 differential / 4 single-ended clock inputs
• Support frequencies from 0.5Hz to 1GHz
• Any input can be mapped to any or all of the timing channels
• Redundant inputs frequency independent of each other
• Any input can be designated as external frame/sync pulse of
PPES (pulse per even second), 1 PPS (Pulse per Second),
5PPS, 10 PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8kHz
associated with a selectable reference clock input
Typical Applications
▪ Core and access IP switches / routers
▪ Synchronous Ethernet equipment
▪ Telecom Boundary Clocks (T-BCs) and Telecom Time Slave
Clocks (T-TSCs) according to ITU-T G.8273.2
▪ 10Gb, 40Gb, and 100Gb Ethernet interfaces
▪ Central Office Timing Source and Distribution
▪ Wireless infrastructure for 4.5G and 5G network equipment
• Per-input programmable phase offset of up to ±1.638s in
1ps steps
▪ Reference monitors qualify/disqualify references depending on
LOS, activity, frequency monitoring, and/or LOS input pins
Features
• Loss of Signal (LOS) input pins (via GPIOs) can be assigned
to any input clock reference
▪ Four independent timing channels
• Each can act as a frequency synthesizer, jitter attenuator,
Digitally Controlled Oscillator (DCO), or Digital Phase Lock
Loop (DPLL)
▪ Automatic reference selection state machines select the active
reference for each DPLL based on the reference monitors,
priority tables, revertive / non-revertive, and other
programmable settings
• DPLLs generate telecom compliant clocks
▪ Compliant with ITU-T G.8262 for Synchronous Ethernet
▪ Compliant with ITU-T G.8262.1 for enhanced
Synchronous Ethernet
▪ System APLL operates from fundamental-mode crystal: 25MHz
to 54MHz or from a crystal oscillator
▪ System DPLL accepts an XO, TCXO, or OCXO operating at
virtually any frequency from 1MHz to 150MHz
▪ Compliant with legacy SONET/SDH and PDH
requirements
▪ DPLLs can be configured as DCOs to synthesize Precision
Time Protocol (PTP) / IEEE 1588 clocks
• DPLL Digital Loop Filters (DLFs) are programmable with cut
off frequencies from 0.09mHz to 12kHz
• DCOs generate PTP based clocks with frequency resolution
less than 1.11 × 10-16
• DPLL/DCO channels share frequency information using the
Combo Bus to simplify compliance with ITU-T G.8273.2
▪ DPLL Phase detectors can be used as Time-to-Digital
Converters (TDC) with 20ps accuracy
▪ Supports 1MHz I2C or 50MHz SPI serial processor ports
• Switching between DPLL and DCO modes is hitless and
dynamic
▪ Automatic reference switching between DCO and DPLL
modes to simplify support for an external phase/time input
interface in a T-BC
▪ The device can configure itself automatically after reset via:
• Internal customer definable One-Time Programmable
memory with up to 16 different configurations
• Standard external I2C EPROM via separate I2C Master Port
▪ 1149.1 JTAG Boundary Scan
• Generates output frequencies that are independent of input
frequencies via a Fractional Output Divider (FOD)
• Each FOD supports output phase tuning with 1ps resolution
©2020-2023 Renesas Electronics Corporation
▪ 72-QFN package, 10 × 10 mm
1
October 10, 2023
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