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87C51FC/BMA-T PDF预览

87C51FC/BMA-T

更新时间: 2024-11-27 13:05:03
品牌 Logo 应用领域
恩智浦 - NXP 微控制器
页数 文件大小 规格书
22页 274K
描述
IC 8-BIT, OTPROM, MICROCONTROLLER, CQCC44, Microcontroller

87C51FC/BMA-T 技术参数

生命周期:Obsolete包装说明:QCCJ,
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.31.00.01风险等级:5.67
具有ADC:NO地址总线宽度:16
位大小:8最大时钟频率:12 MHz
DAC 通道:NODMA 通道:NO
外部数据总线宽度:8JESD-30 代码:S-GQCC-J44
I/O 线路数量:32端子数量:44
最高工作温度:125 °C最低工作温度:-55 °C
PWM 通道:YES封装主体材料:CERAMIC, GLASS-SEALED
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER认证状态:Not Qualified
ROM可编程性:OTPROM标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:J BEND
端子位置:QUADuPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

87C51FC/BMA-T 数据手册

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Philips Semiconductors  
Product specification  
CMOS single-chip 8-bit microcontrollers  
80C31/80C51/87C51  
DESCRIPTION  
PIN CONFIGURATIONS  
The Philips 80C31/80C51/87C51 is a high-performance  
microcontroller fabricated with Philips high-density CMOS  
technology. The CMOS 8XC51 is functionally compatible with the  
NMOS 8031/8051 microcontrollers. The Philips CMOS technology  
combines the high speed and density characteristics of HMOS with  
the low power attributes of CMOS. Philips epitaxial substrate  
minimizes latch-up sensitivity.  
P1.0  
P1.1  
40  
V
1
2
3
CC  
P0.0/AD0  
P0.1/AD1  
39  
38  
P1.2  
37 P0.2/AD2  
36  
P1.3  
P1.4  
4
5
P0.3/AD3  
35 P0.4/AD4  
34  
The 8XC51 contains a 4k × 8 ROM (80C51) EPROM (87C51), a 128  
× 8 RAM, 32 I/O lines, two 16-bit counter/timers, a five-source,  
two-priority level nested interrupt structure, a serial I/O port for either  
multi-processor communications, I/O expansion or full duplex UART,  
and on-chip oscillator and clock circuits.  
P1.5  
P1.6  
P1.7  
RST  
6
7
8
9
P0.5/AD5  
33 P0.6/AD6  
32  
31  
30  
P0.7/AD7  
CERAMIC  
AND  
PLASTIC  
DUAL  
IN-LINE  
PACKAGE  
In addition, the device has two software selectable modes of power  
reduction—idle mode and power-down mode. The idle mode freezes  
the CPU while allowing the RAM, timers, serial port, and interrupt  
system to continue functioning. The power-down mode saves the  
RAM contents but freezes the oscillator, causing all other chip  
functions to be inoperative.  
EA/V  
PP  
RxD/P3.0 10  
TxD/P3.1 11  
INT0/P3.2 12  
ALE/PROG  
29 PSEN  
13  
28 P2.7/A15  
27 P2.6/A14  
INT1/P3.3  
T0/P3.4 14  
T1/P3.5 15  
WR/P3.6 16  
RD/P3.7 17  
XTAL2 18  
XTAL1 19  
26  
P2.5/A13  
FEATURES  
25 P2.4/A12  
24 P2.3/A11  
8031/8051 compatible  
4k × 8 ROM (80C51)  
4k × 8 EPROM (87C51)  
ROMless (80C31)  
23  
22  
21  
P2.2/A10  
P2.1/A9  
P2.0/A8  
128 × 8 RAM  
20  
V
SS  
Two 16-bit counter/timers  
Full duplex serial channel  
Boolean processor  
6
1
40  
Memory addressing capability  
64k ROM and 64k RAM  
7
39  
29  
CERAMIC  
AND  
PLASTIC  
LEAD  
CHIP  
CARRIER  
Power control modes:  
Idle mode  
17  
Power-down mode  
CMOS and TTL compatible  
18  
28  
34  
Five speed ranges at V = 5V  
CC  
12MHz  
16MHz  
24MHz  
33MHz  
44  
1
33  
23  
PLASTIC  
QUAD  
FLAT  
Five package styles  
PACK  
Extended temperature ranges  
OTP package available  
11  
12  
22  
SU00001  
SEE PAGE 3-6 FOR QFP AND LCC PIN FUNCTIONS.  
3-3  
1996 Aug 16  
853–0169 17187  

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