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8633AF-01 PDF预览

8633AF-01

更新时间: 2024-11-11 20:54:19
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
16页 291K
描述
PLL Based Clock Driver, 8633 Series, 3 True Output(s), 0 Inverted Output(s), PDSO28, 5.30 X 10.20 MM, 1.75 MM HEIGHT, MO-150, SSOP-28

8633AF-01 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP28,.3针数:28
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.7
系列:8633输入调节:DIFFERENTIAL MUX
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:10.2 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:28
实输出次数:3最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP28,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):225电源:3.3 V
Prop。Delay @ Nom-Sup:4.9 ns传播延迟(tpd):4.9 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.025 ns
座面最大高度:2 mm子类别:Clock Driver
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:5.3 mmBase Number Matches:1

8633AF-01 数据手册

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ICS8633-01  
1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL  
ZERO DELAY BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS8633-01 is  
a
high performance 1-to-3  
Three differential 3.3V LVPECL outputs  
Selectable differential clock inputs  
Differential-to-3.3V LVPECL Zero Delay Buffer. The  
ICS8633-01 has two selectable clock inputs. The CLKx,  
nCLKx pairs can accept most standard differential input  
levels. Utilizing one of the outputs as feedback to the PLL,  
output frequencies up to 700MHz can be regenerated with  
zero delay with respect to the input. Dual reference clock  
inputs support redundant clock or multiple reference  
applications.  
CLKx, nCLKx pairs can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL  
Output frequency range: 31.25MHz to 700MHz  
Input frequency range: 31.25MHz to 700MHz  
VCO range: 250MHz to 700MHz  
External feedback for “zero delay” clock regeneration  
Cycle-to-cycle jitter: 25ps (maximum)  
Output skew: 25ps (maximum)  
PLL reference zero delay: 50ps 100ps  
3.3V operating supply  
0°C to 70°C ambient operating temperature  
Industrial temperature information available upon request  
Available in both standard and lead-free RoHs-compliant  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
PLL_SEL  
Q0  
1
2
3
4
PLL_SEL  
VCC  
28  
27  
26  
25  
VCCA  
VEE  
VEE  
VCCO  
VCCO  
Q2  
nQ2  
Q1  
nQ0  
÷4, ÷8  
0
CLK0  
nCLK0  
SEL0  
SEL1  
Q1  
nQ1  
0
1
1
CLK0  
nCLK0  
CLK1  
24  
23  
22  
21  
20  
19  
5
6
7
8
CLK1  
nCLK1  
Q2  
nQ2  
PLL  
nCLK1  
CLK_SEL  
CLK_SEL  
MR  
nQ1  
Vcco  
Vcco  
Q0  
nQ0  
VEE  
9
10  
11  
12  
13  
FB_IN  
nFB_IN  
VCC  
18  
17  
16  
15  
nFB_IN  
FB_IN  
VEE  
14  
SEL0  
SEL1  
MR  
ICS8633-01  
28-Lead, 209-MIL SSOP  
5.3mm x 10.2mm x 1.75mm body package  
F Package  
Top View  
8633AF-01  
www.idt.com  
REV. B AUGUST 2, 2010  
1

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