Datasheet > 854S006I

854S006I

更新时间： 2023-12-20 18:44:11

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
18页	1090K
描述
Low Skew,1-to-6,Differential-to-LVDS Fanout Buffer

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854S006I 数据手册

Low Skew, 1-to-6,

854S006

Differential-to-LVDS Fanout Buffer

Datasheet

Description

Features

The 854S006 is a low skew, high performance 1-to-6,

▪ Six differential LVDS outputs

▪ One differential clock input pair

Differential-to-LVDS fanout buffer. The CLK, nCLK pair can accept

most standard differential input levels. The 854S006 is

characterized to operate from either a 2.5V or a 3.3V power

supply. Guaranteed output and part-to-part skew characteristics

make the 854S006 ideal for those clock distribution applications

demanding well defined performance and repeatability.

▪ CLK, nCLK pair can accept the following differential input

levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL

▪ Maximum output frequency: 1.7GHz

▪ Translates any single-ended input signal to LVDS levels with

resistor bias on nCLK input

▪ Output Skew: 55ps (maximum)

▪ Propagation delay: 850ps (maximum)

▪ Additive phase jitter, RMS: 0.067ps (typical)

▪ Full 3.3V or 2.5V supply

▪ -40°C to 85°C ambient operating temperature

▪ Available in lead-free (RoHS 6) package

Block Diagram

Pin Assignment

nCLK

CLK

V_DD

GND

V_DD

nQ0

Pull-up

CLK

nCLK

Pull-down

nQ1

V_DDO

nQ5

nQ0

GND

nQ2

GND

nQ4

nQ3

nQ1

V_DDO

nQ3

nQ4

nQ2

nQ5

April 11, 2017

12 3 4 5 6 7...18

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