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8543BGIT PDF预览

8543BGIT

更新时间: 2024-11-13 21:15:43
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
18页 855K
描述
Low Skew Clock Driver, 8543 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 4.40 X 6.50 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20

8543BGIT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:4.40 X 6.50 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20针数:20
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.65
系列:8543输入调节:DIFFERENTIAL MUX
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:6.5 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:20
实输出次数:4最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):225
电源:3.3 VProp。Delay @ Nom-Sup:2.6 ns
传播延迟(tpd):2.6 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.04 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

8543BGIT 数据手册

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LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS  
FANOUT BUFFER  
ICS8543I  
General Description  
Features  
The ICS8543I is a low skew, high performance  
Four differential LVDS output pairs  
S
IC  
1-to-4 Differential-to-LVDS Clock Fanout Buffer and  
a member of the HiPerClockS™ family of High  
Performance Clock Solutions from IDT. Utilizing Low  
Voltage Differential Signaling (LVDS) the ICS8543I  
Selectable differential CLK/nCLK or LVPECL clock inputs  
HiPerClockS™  
CLK/nCLK pair can accept the following differential input levels:  
LVPECL, LVDS, LVHSTL, SSTL, HCSL  
PCLK/nPCLK pair can accept the following differential input  
provides a low power, low noise, solution for distributing clock  
signals over controlled impedances of 100. The ICS8543I has  
two selectable clock inputs. The CLK, nCLK pair can accept most  
standard differential input levels. The PCLK, nPCLK pair can  
accept LVPECL, CML, or SSTL input levels. The clock enable is  
internally synchronized to eliminate runt pulses on the outputs  
during asynchronous assertion/deassertion of the clock enable  
pin.  
levels: LVPECL, CML, SSTL  
Maximum output frequency: 650MHz  
Translates any single-ended input signals to LVDS levels with  
resistor bias on nCLK input  
Additive phase Jitter, RMS: 0.164ps (typical)  
Output skew: 40ps (maximum)  
Part-to-part skew: 600ps (maximum)  
Propagation delay: 2.6ns (maximum)  
Full 3.3Vsupply mode  
Guaranteed output and part-to-part skew characteristics make the  
ICS8543I ideal for those applications demanding well defined  
performance and repeatability.  
-40°C to 85°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
Pin Assignment  
Block Diagram  
GND  
CLK_EN  
CLK_SEL  
CLK  
1
2
20 Q0  
Pullup  
CLK_EN  
D
19  
nQ0  
Q
3
4
18  
17  
VDD  
Q1  
LE  
Pulldown  
Pullup  
CLK  
nCLK  
0
nCLK  
PCLK  
nPCLK  
5
6
7
8
9
16 nQ1  
Q0  
15  
14  
13  
Q2  
nQ2  
GND  
nQ0  
Pulldown  
Pullup  
PCLK  
nPCLK  
1
Q1  
nQ1  
OE  
GND  
VDD 10  
12 Q3  
11  
nQ3  
Pulldown  
CLK_SEL  
Q2  
nQ2  
ICS8543I  
Q3  
20-Lead TSSOP  
6.5mm x 4.4mm x 0.925mm  
package body  
nQ3  
Pullup  
OE  
G Package  
Top View  
IDT™ / ICS™ LVDS FANOUT BUFFER  
1
ICS8543BGI REV. E SEPTEMBER 9, 2008  

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