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854058AGT PDF预览

854058AGT

更新时间: 2024-09-24 19:48:55
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管逻辑集成电路
页数 文件大小 规格书
12页 1687K
描述
Multiplexer, 854058 Series, 1-Func, 8 Line Input, 1 Line Output, Complementary Output, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MS-153, TSSOP-24

854058AGT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:4.40 X 7.80 MM, 0.92 MM HEIGHT, MS-153, TSSOP-24
针数:24Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.84
系列:854058JESD-30 代码:R-PDSO-G24
长度:7.8 mm逻辑集成电路类型:MULTIPLEXER
功能数量:1输入次数:8
输出次数:1端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):225
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

854058AGT 数据手册

 浏览型号854058AGT的Datasheet PDF文件第2页浏览型号854058AGT的Datasheet PDF文件第3页浏览型号854058AGT的Datasheet PDF文件第4页浏览型号854058AGT的Datasheet PDF文件第5页浏览型号854058AGT的Datasheet PDF文件第6页浏览型号854058AGT的Datasheet PDF文件第7页 
PRELIMINARY  
ICS854058  
Integrated  
Circuit  
Systems, Inc.  
8:1  
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER  
GENERAL DESCRIPTION  
FEATURES  
The ICS854058 is an 8:1 Differential-to-LVDS Clock High speed 8:1 differential multiplexer  
ICS  
Multiplexer which can operate up to 2.5GHz and  
is a member of the HiPerClockSfamily of High  
Performance Clock Solutions from ICS. The  
ICS854058 has 8 selectable differential clock in-  
1 differential LVDS output  
HiPerClockS™  
8 selectable differential PCLK, nPCLK inputs  
PCLKx, nPCLKx pairs can accept the following  
differential input levels: LVPECL, LVDS, CML, SSTL  
puts.The PCLK, nPCLK input pairs can accept LVPECL, LVDS,  
CML or SSTL levels.The fully differential architecture and low  
propagation delay make it ideal for use in clock distribution cir-  
cuits.The select pins have internal pulldown resistors.The SEL2  
pin is the most significant bit and the binary number applied to  
the select pins will select the same numbered data input (i.e.,  
000 selects PCLK0, nPCLK0).  
Maximum output frequency: 2.5GHz  
Translates any single ended input signal to  
LVDS levels with resistor bias on nPCLKx input  
Part-to-part skew: TBD  
Propagation delay: 595ps (typical)  
Supply voltage range: 3.135V to 3.465V  
-40°C to 85°C ambient operating temperature  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
1
2
3
4
5
6
7
8
24  
PCLK0  
nPCLK0  
PCLK1  
nPCLK1  
VDD  
SEL0  
SEL1  
SEL2  
PCLK2  
nPCLK2  
PCLK3  
nPCLK3  
PCLK7  
23 nPCLK7  
22 PLCK6  
21 nPCLK6  
PCLK0  
000  
nPCLK0  
20  
19  
18  
17  
16  
15  
14  
13  
VDD  
Q0  
nQ0  
GND  
PCLK5  
nPCLK5  
PCLK4  
nPCLK4  
PCLK1  
001  
nPCLK1  
PCLK2  
010  
9
nPCLK2  
10  
11  
12  
PCLK3  
011  
nPCLK3  
Q0  
nQ0  
PCLK4  
100  
ICS854058  
24-Lead, 173-MIL TSSOP  
4.4mm x 7.8mm x 0.92mm body package  
G Package  
nPCLK4  
PCLK5  
101  
nPCLK5  
Top View  
PCLK6  
110  
nPCLK6  
PCLK7  
111  
nPCLK7  
SEL0  
SEL1  
SEL2  
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
854058AG  
www.icst.com/products/hiperclocks.html  
REV. A OCTOBER 29, 2008  
1

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