Datasheet > 8533-01

8533-01

更新时间： 2024-10-03 14:58:15

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
18页	406K
描述
Low Skew,1-to-4 Differential-to-3.3V LVPECL Fanout Buffer

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8533-01 数据手册

Low Skew, 1-to-4

Differential-to-3.3V LVPECL Fanout Buffer

8533-01

Data Sheet

GENERAL DESCRIPTION

FEATURES

The 8533-01 is a low skew, high performance 1-to-4 • Four differential 3.3V LVPECL outputs

Differential-to-3.3V LVPECL Fanout Buffer. The 8533-

• Selectable differential CLK, nCLK or LVPECL clock inputs

01 has two selectable clock inputs. The CLK, nCLK pair

can accept most standard differential input levels. The

PCLK, nPCLK pair can accept LVPECL, CML, or SSTL

input levels. The clock enable is internally synchronized to

eliminate runt pulses on the outputs during asynchronous

assertion/deassertion of the clock enable pin. Guaranteed

output and part-to-part skew characteristics make the 8533-01

ideal for those applications demanding well deﬁned performance

and repeatability.

• CLK, nCLK pair can accept the following differential

input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL

• PCLK, nPCLK supports the following input types:

LVPECL, CML, SSTL

• Maximum output frequency: 650MHz

• Translates any single-ended input signal to 3.3V

LVPECL levels with resistor bias on nCLK input

• Output skew: 30ps (maximum)

• Part-to-part skew: 150ps (maximum)

• Propagation delay: 1.4ns (maximum)

• Additive phase jitter, RMS: 0.06ps (typical)

• 3.3V operating supply

• 0°C to 70°C ambient operating temperature

• Lead-Free package

• Industrial temperature information available upon request

BLOCK DIAGRAM

PIN ASSIGNMENT

8533-01

20-Lead TSSOP

6.5mm x 4.4mm x 0.92mm package body

G Package

Top View

Revision F January 19, 2016

12 3 4 5 6 7...18

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