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8516FYILF PDF预览

8516FYILF

更新时间: 2024-01-24 03:18:44
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
18页 181K
描述
Low Skew, 1-to-16 Differential-to-LVDS, Clock Distribution Chip

8516FYILF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Lifetime Buy零件包装代码:TQFP
包装说明:LQFP-48针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.42
系列:8516输入调节:DIFFERENTIAL
JESD-30 代码:S-PQFP-G48JESD-609代码:e3
长度:7 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:48
实输出次数:32最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP48,.35SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:2.4 ns
传播延迟(tpd):2.4 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.065 ns座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
最小 fmax:700 MHzBase Number Matches:1

8516FYILF 数据手册

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Low Skew, 1-to-16 Differential-to-  
LVDS, Clock Distribution Chip  
ICS8516I  
DATA SHEET  
GENERAL DESCRIPTION  
FEATURES  
Sixteen Differential LVDS outputs  
The ICS8516I is a low skew, high performance 1-  
to-16 Differential-to-LVDS Clock Distribution Chip  
and a member of the HiPerClockS™ family of High  
Performance Clock Solutions from IDT. The  
ICS8516I CLK, nCLK pair can accept any differ-  
ICS  
HiPerClockS™  
CLK, nCLK pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL  
Maximum output frequency: 700MHz  
ential input levels and translates them to 3.3V LVDS output  
levels. Utilizing Low Voltage Differential Signaling (LVDS), the  
ICS8516I provides a low power, low noise, point-to-point solu-  
tion for distributing clock signals over controlled impedances  
of 100.  
Translates any differential input signal (LVPECL, LVHSTL,  
SSTL, DCM) to LVDS levels without external bias networks  
Translates any single-ended input signal to LVDS  
with resistor bias on nCLK input  
Dual output enable inputs allow the ICS8516I to be used in a  
1-to-16 or 1-to-8 input/output mode. Guaranteed output and  
part-to-part skew specifications make the ICS8516I ideal for  
those applications demanding well defined performance and  
repeatability.  
Multiple output enable inputs for disabling unused  
outputs in reduced fanout applications  
LVDS compatible  
Output skew: 65ps (maximum)  
Part-to-part skew: 550ps (maximum)  
Propagation delay: 2.4ns (maximum)  
3.3V operating supply  
-40°C to 85°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
CLK  
nCLK  
48 47 46 45 44 43 42 41 40 39 38 37  
VDD  
nQ5  
Q5  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDD  
Q0  
nQ0  
Q15  
nQ15  
2
nQ10  
Q10  
nQ11  
Q11  
VDD  
3
Q1  
nQ1  
Q14  
nQ14  
nQ4  
Q4  
4
5
Q2  
nQ2  
Q13  
nQ13  
VDD  
GND  
nQ3  
Q3  
6
ICS8516I  
7
GND  
nQ12  
Q12  
nQ13  
Q13  
VDD  
8
Q12  
nQ12  
Q3  
nQ3  
9
nQ2  
Q2  
10  
11  
12  
Q4  
nQ4  
Q11  
nQ11  
VDD  
13 14 15 16 17 18 19 20 21 22 23 24  
Q10  
nQ10  
Q5  
nQ5  
Q9  
nQ9  
Q6  
nQ6  
Q8  
nQ8  
Q7  
nQ7  
48-Lead LQFP  
7mm x 7mm x 1.4mm body package  
Y Package  
Top View  
OE1  
OE2  
ICS8516I REVISION B SEPTEMBER 10, 2009  
1
2009 Integrated Device Technology, Inc.  

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