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85102AGILF PDF预览

85102AGILF

更新时间: 2024-02-02 12:46:56
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
17页 244K
描述
Low Skew, 1-to-2, Differential/LVCMOS HCSL Fanout Buffer

85102AGILF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.03
系列:85102输入调节:DIFFERENTIAL MUX
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:5 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:16
实输出次数:2最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:3.2 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):2.97 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

85102AGILF 数据手册

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85102  
Low Skew, 1-to-2, Differential/LVCMOS-  
to-0.7V HCSL Fanout Buffer  
DATA SHEET  
GENERAL DESCRIPTION  
FEATURES  
The 85102I is a low skew, high performance 1-to-2 Differen-  
tial-to-HCSL fanout buffer.The 85102I has a differential clock input.  
The CLK0, nCLK0 input pair can accept most standard differential  
input levels.The clock enable is internally synchronized to eliminate  
runt clock pulses on the output during asynchronous assertion/  
deassertion of the clock enable pin.  
Two 0.7V differential HCSL outputs  
Selectable differential CLK0, nCLK0 or LVCMOS inputs  
CLK0, nCLK0 pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, HCSL  
CLK1 can accept the following input levels:  
LVCMOS or LVTTL  
Guaranteed output and part-to-part skew characteristics  
make the 85102I ideal for those applications demanding well defined  
performance and repeatability.  
Maximum output frequency: 500MHz  
Translates any single-ended input signal to 3.3V  
HCSL levels with resistor bias on nCLK input  
Output skew: 65ps (maximum)  
Part-to-part skew: 600ps (maximum)  
Propagation delay: 3.2ns (maximum)  
Additive phase jitter, RMS: 0.14ps typical @ 250MHz  
3.3V operating supply  
-40°C to 85°C ambient operating temperature  
Available in lead-free (RoHS 6) package  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CLK_EN  
CLK_SEL  
CLK0  
nCLK0  
CLK1  
nc  
GND  
VDD  
Q0  
nQ0  
Q1  
nQ1  
VDD  
VDD  
Pullup  
CLK_EN  
D
Q
Pulldown  
Pullup/Pulldown  
LE  
CLK0  
nCLK0  
0
1
Q0  
nQ0  
nc  
IREF  
Pulldown  
Pulldown  
CLK1  
Q1  
nQ1  
CLK_SEL  
IREF  
85102I  
16-Lead TSSOP  
4.4mm x 5.0mm x 0.925mm body package  
G Package  
Top View  
85102 REVISION B DECEMBER 19, 2014  
1
©2014 Integrated Device Technology, Inc.  

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