Datasheet > 85102

85102

更新时间： 2024-02-16 12:08:15

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
17页	244K
描述
Low Skew, 1-to-2, Differential/LVCMOS HCSL Fanout Buffer

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技术参数
数据手册

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85102 技术参数

生命周期：	Transferred	Reach Compliance Code：	unknown
风险等级：	5.27	其他特性：	STANDARD: MIL-C-26482, MAX CONTACTS (SERIES)=61
后壳类型：	SOLID	主体/外壳类型：	RECEPTACLE
连接器类型：	MIL SERIES CONNECTOR	触点性别：	FEMALE; MALE
耦合类型：	BAYONET	DIN 符合性：	NO
空壳：	NO	环境特性：	ENVIRONMENT/VIBRATION RESISTANT
滤波功能：	NO	IEC 符合性：	NO
MIL 符合性：	YES	插接信息：	MULTIPLE MATING PARTS AVAILABLE
混合触点：	NO	安装类型：	PANEL
选件：	GENERAL PURPOSE	外壳面层：	CADMIUM PLATED
外壳材料：	ALUMINUM ALLOY	外壳尺寸：	8; 10; 12; 14; 16; 18; 20; 22; 24
端接类型：	SOLDER	Base Number Matches：	1

85102 数据手册

85102

Low Skew, 1-to-2, Differential/LVCMOS-

to-0.7V HCSL Fanout Buffer

DATA SHEET

GENERAL DESCRIPTION

FEATURES

The 85102I is a low skew, high performance 1-to-2 Differen-

tial-to-HCSL fanout buffer.The 85102I has a differential clock input.

The CLK0, nCLK0 input pair can accept most standard differential

input levels.The clock enable is internally synchronized to eliminate

runt clock pulses on the output during asynchronous assertion/

deassertion of the clock enable pin.

• Two 0.7V differential HCSL outputs

• Selectable differential CLK0, nCLK0 or LVCMOS inputs

• CLK0, nCLK0 pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL

• CLK1 can accept the following input levels:

LVCMOS or LVTTL

Guaranteed output and part-to-part skew characteristics

make the 85102I ideal for those applications demanding well deﬁned

performance and repeatability.

• Maximum output frequency: 500MHz

• Translates any single-ended input signal to 3.3V

HCSL levels with resistor bias on nCLK input

• Output skew: 65ps (maximum)

• Part-to-part skew: 600ps (maximum)

• Propagation delay: 3.2ns (maximum)

• Additive phase jitter, RMS: 0.14ps typical @ 250MHz

• 3.3V operating supply

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package

BLOCK DIAGRAM

PIN ASSIGNMENT

CLK_EN

CLK_SEL

CLK0

nCLK0

CLK1

GND

V^DD

nQ0

nQ1

V^DD

VDD

Pullup

CLK_EN

Pulldown

Pullup/Pulldown

CLK0

nCLK0

nQ0

IREF

Pulldown

CLK1

nQ1

CLK_SEL

IREF

85102I

16-Lead TSSOP

4.4mm x 5.0mm x 0.925mm body package

G Package

Top View

85102 REVISION B DECEMBER 19, 2014

12 3 4 5 6 7...17

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