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8431AM-21 PDF预览

8431AM-21

更新时间: 2024-01-18 17:45:09
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管外围集成电路
页数 文件大小 规格书
19页 296K
描述
Clock Generator, CMOS, PDSO28

8431AM-21 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:ObsoleteReach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.92JESD-30 代码:R-PDSO-G28
JESD-609代码:e0湿度敏感等级:1
端子数量:28最高工作温度:85 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP28,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified子类别:Clock Generators
最大压摆率:155 mA标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

8431AM-21 数据手册

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ICS8431-21  
350MHZ, Low Jitter, Crystal Oscillator-to-3.3V  
LVPECL Frequency Synthesizer  
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES ON (JULY 26, 2014)  
GENERAL DESCRIPTION  
FEATURES  
Fully integrated PLL  
The ICS8431-21 is a general purpose clock frequency synthe-  
sizer for IA64/32 application. The VCO operates at a frequency  
range of 250MHz to 700MHz providing an output frequency range  
of 62.5MHz to 350MHz.The output frequency can be programmed  
using the parallel interface, M0 through M8 to the configuration  
logic, and the output divider control pin, DIV_SEL. Spread spec-  
trum clocking is programmed via the control inputs SSC_CTL0  
and SSC_CTL1.  
Differential 3.3V LVPECL output  
Crystal oscillator interface  
Output frequency range: 62.5MHz to 350MHz  
Crystal input frequency range: 14MHz to 25MHz  
VCO range: 250MHz to 700MHz  
Programmable features of the ICS8431-21 support four opera-  
tional modes. The four modes are spread spectrum clocking  
(SSC), non-spread spectrum clock and two test modes which are  
controlled by the SSC_CTL[1:0] pins. Unlike other synthesizers,  
the ICS8431-21 can immediately change spread-spectrum op-  
eration without having to reset the device.  
Programmable PLL loop divider for generating a variety  
of output frequencies  
Spread Spectrum Clocking (SSC) fixed at 1/2% modulation for  
environments requiring ultra low EMI  
PLL bypass modes supporting in-circuit testing and on-chip  
functional block characterization  
In SSC mode, the output clock is modulated in order to achieve a  
reduction in EMI. In one of the PLL bypass test modes, the PLL is  
disconnected as the source to the differential output allowing an  
external source to be connected to the TEST_I/O pin.This is use-  
ful for in-circuit testing and allows the differential output to be  
driven at a lower frequency throughout the system clock tree. In  
the other PLL bypass mode, the oscillator divider is used as the  
source to both the M and the Fout divide by 2. This is useful for  
characterizing the oscillator and internal dividers.  
Cycle-to-cycle jitter: 30ps (maximum)  
3.3V supply voltage  
0°C to 85°C ambient operating temperature  
Replaces ICS8431-01 and ICS8431-11  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
Use Replacement Part: 84314AY-02LF  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
M0  
M1  
M2  
M3  
M4  
M5  
M6  
M7  
M8  
1
2
3
4
5
6
7
8
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
nP_LOAD  
XTAL_IN  
OSC  
XTAL_OUT  
V
CC  
XTAL_IN  
XTAL_OUT  
nc  
÷ 16  
nc  
V
V
CCA  
EE  
PLL  
9
MR  
DIV_SEL  
PHASE  
DETECTOR  
SSC_CTL0  
SSC_CTL1  
10  
11  
12  
13  
14  
V
CCO  
÷2  
V
FOUT  
nFOUT  
VCO  
EE  
÷4  
TEST_I/O  
FOUT  
nFOUT  
V
V
CC  
EE  
÷ M  
ICS8431-21  
28-Lead SOIC  
TEST_I/O  
7.5mm x 18.05mm x 2.25mm package body  
M Package  
Top View  
SSC  
Control  
Logic  
Configuration  
Logic  
M0:M8  
nP_LOAD  
SSC_CTL0  
SSC_CTL1  
DIV_SEL  
IDT/ ICS3.3V LVPECL FREQUENCY SYNTHESIZER  
1
ICS8431AM-21 REV. B AUGUST 22, 2013  

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