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84314AYT PDF预览

84314AYT

更新时间: 2024-11-11 19:15:47
品牌 Logo 应用领域
艾迪悌 - IDT 时钟外围集成电路晶体
页数 文件大小 规格书
19页 432K
描述
Clock Generator, PQFP32

84314AYT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:LQFP-32
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.53
JESD-30 代码:S-PQFP-G32JESD-609代码:e0
长度:7 mm湿度敏感等级:3
端子数量:32最高工作温度:85 °C
最低工作温度:最大输出时钟频率:350 MHz
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP32,.35SQ,32封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):225
电源:3.3 V主时钟/晶体标称频率:40 MHz
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:Clock Generators最大压摆率:150 mA
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:7 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

84314AYT 数据手册

 浏览型号84314AYT的Datasheet PDF文件第2页浏览型号84314AYT的Datasheet PDF文件第3页浏览型号84314AYT的Datasheet PDF文件第4页浏览型号84314AYT的Datasheet PDF文件第5页浏览型号84314AYT的Datasheet PDF文件第6页浏览型号84314AYT的Datasheet PDF文件第7页 
DATA SHEET  
ICS84314  
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY  
SYNTHESIZER W/FANOUT BUFFER  
FEATURES  
GENERAL DESCRIPTION  
Fully integrated PLL  
The ICS84314 is a general purpose quad output  
ICS  
frequency synthesizer and a member of the  
4 differential 3.3V or 2.5V LVPECL outputs  
HiPerClockS™  
HiPerClockS™ family of High Performance Clock  
Solutions from ICS. When the device uses par- Selectable crystal oscillator interface  
allel loading, the M bits are programmable and  
the output divider is hard-wired for divide by 2 thus providing  
a frequency range of 125MHz to 350MHz. In serial program-  
ming mode, the M bits are programmable and the output di-  
vider can be set for either divide by 2 or divide by 4, providing  
a frequency range of 62.5MHz to 350MHz. The low cycle-  
cycle jitter and broad frequency range of the ICS84314 make  
it an ideal clock generator for a variety of demanding applica-  
tions which require high performance.  
or LVCMOSTEST_CLK input  
Output frequency range: 62.5MHz to 350MHz  
VCO range: 250MHz to 700MHz  
Parallel interface for programming counter  
and output dividers during power-up  
Serial 3 wire interface  
Cycle-to-cycle jitter: 23ps (typical)  
Output skew: 16ps (typical)  
Output duty cycle: 49% < odc < 51%, fout 125MHz  
Full 3.3V or mixed 3.3V core, 2.5V operating supply  
0°C to 85°C ambient operating temperature  
Lead-Free package available  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
VCO_SEL  
XTAL_SEL  
32 31 30 29 28 27 26 25  
M4  
M5  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
TEST_CLK  
XTAL_SEL  
VCCA  
TEST_CLK  
0
M6  
XTAL1  
1
OSC  
M7  
S_LOAD  
S_DATA  
S_CLOCK  
MR  
XTAL2  
ICS84314  
M8  
÷ 16  
VEE  
VCC  
VCCO  
VCCO  
PLL  
Q0  
nQ0  
PHASE DETECTOR  
9
10 11 12 13 14 15 16  
Q1  
nQ1  
MR  
0
VCO  
÷2  
÷4  
Q2  
nQ2  
÷ M  
1
÷2  
Q3  
nQ3  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
S_LOAD  
S_DATA  
S_CLOCK  
Y Package  
TopView  
CONFIGURATION  
INTERFACE  
LOGIC  
nP_LOAD  
M0:M8  
IDT™ / ICS™ 350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER  
ICS84314  
1

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