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843001AG-21T PDF预览

843001AG-21T

更新时间: 2024-11-01 14:50:03
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
17页 2674K
描述
Clock Generator, 700MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24

843001AG-21T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24针数:24
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.82
JESD-30 代码:R-PDSO-G24JESD-609代码:e0
长度:7.8 mm湿度敏感等级:1
端子数量:24最高工作温度:70 °C
最低工作温度:最大输出时钟频率:700 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP24,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):240
电源:3.3 V主时钟/晶体标称频率:40 MHz
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Clock Generators最大压摆率:170 mA
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

843001AG-21T 数据手册

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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL  
FREQUENCY SYNTHESIZER  
ICS843001-21  
Description  
Features  
The ICS843001-21 is a a highly versatile, low  
One 3.3Vdifferential LVPECL output pair and  
S
one LVCMOS/LVTTL single-ended reference clock output  
IC  
phase noise LVPECL Synthesizer which can  
generate low jitter reference clocks for a variety of  
communications applications and is a member of  
HiPerClockS™  
Selectable crystal oscillator interface  
or LVCMOS/LVTTL single-ended input  
TM  
the HiPerClocks family of high performance clock  
VCO range: 560MHz – 700MHz  
solutions from IDT. The dual crystal interface allows the  
synthesizer to support up to two communications standards in a  
given application (i.e. 1GB Ethernet with a 25MHz crystal and 1Gb  
Fibre Channel using a 26.5625MHz crystal). The rms phase jitter  
performance is typically less than 1ps, thus making the device  
acceptable for use in demanding applications such as OC48  
SONET and 10Gb Ethernet. The ICS843001-21 is packaged in a  
small 24-pin TSSOP package.  
Supports the following applications:  
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV  
Selectable ÷1 or ÷2 operation  
RMS phase jitter @ 622.08MHz (12kHz - 20MHz):  
0.80ps (typical)  
Offset  
Noise Power  
100Hz................ -60.3 dBc/Hz  
1kHz .................. -88.5 dBc/Hz  
10kHz ................ -111.9 dBc/Hz  
100kHz .............. -113.0 dBc/Hz  
Full 3.3V supply mode  
0°C to 70°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
Pin Assignment  
REF_CLK  
1
2
24  
23  
VCCO_CMOS  
Block Diagram  
VEE  
N0  
N1  
N2  
OE_REF  
M2  
3
4
22  
21  
3
N2:N0  
5
6
7
20  
19  
18  
17  
M1  
M0  
MR  
VCCO_PECL  
Q0  
Pulldown  
SEL0  
Q0  
VEE  
Pulldown  
SEL1  
SEL1  
8
9
SEL0  
VCCA  
VCC  
XTAL_OUT1  
XTAL_IN1  
16  
15  
14  
13  
N
TEST_CLK  
XTAL_IN0  
XTAL_OUT0  
10  
11  
12  
000 ÷1  
XTAL_IN0  
001 ÷2  
OSC  
OSC  
00  
11  
010 ÷3  
Q0  
XTAL_OUT0  
XTAL_IN1  
011 ÷4 (default)  
100 ÷5  
ICS843001-21  
10  
01  
00  
Q0  
Phase  
Detector  
24-Lead TSSOP  
VCO  
101 ÷6  
01  
10  
4.4mm x 7.8mm x 0.925mm  
package body  
G Package  
110 ÷8  
111 ÷10  
XTAL_OUT1  
TEST_CLK  
M
Pulldown  
000 ÷18  
Top View  
001 ÷22  
010 ÷24  
011 ÷25  
100 ÷32 (default)  
101 ÷40  
Pulldown  
3
MR  
M2:M0  
REF_CLK  
Pulldown  
OE_REF  
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER  
1
ICS843001AG-21 REV. AMARCH 15, 2007  

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