Datasheet > 8413S12I-126

8413S12I-126

更新时间： 2024-11-05 14:57:55

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
30页	947K
描述
HCSL/LVCMOS Clock Generator

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中文翻译

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数据手册

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8413S12I-126 数据手册

HCSL/ LVCMOS Clock Generator

8413S12BI-126

Data Sheet

General Description

Features

The 8413S12BI-126 is a PLL-based clock generator. This high

performance device is optimized to generate the processor core

reference clock, the PCI-Express, sRIO, XAUI, SerDes reference

clocks and the clocks for both the Gigabit Ethernet MAC and PHY.

The clock generator offers ultra low-jitter, low-skew clock outputs.

The output frequencies are generated from a 25MHz external input

source or an external 25MHz parallel resonant crystal. The industrial

temperature range of the 8413S12BI-126 supports

• Ten selectable 100MHz and 156.25MHz clocks for PCI Express,

sRIO and GbE, HCSL interface levels

• One single-ended QF LVCMOS/LVTTL clock output at 50MHz,

15 output impedance

• Selectable external crystal or differential (single-ended)

input source

• Crystal oscillator interface designed for 25MHz, parallel

resonant crystal

telecommunication, networking, and storage requirements.

• Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,

LVHSTL, HCSL input levels

Applications

• Internal resistor bias on nCLK pin allows the user to drive CLK

input with external single-ended (LVCMOS/ LVTTL) input levels

• CPE Gateway Design

• PCI Express (2.5Gb/S), Gen 2 (5Gb/s) and Gen 3 (8Gb/s)

• Home Media Servers

• 802.11n AP or Gateway

• Soho Secure Gateway

• Soho SME Gateway

• Wireless Soho and SME VPN Solutions

• Wired and Wireless Network Security

jitter compliant

• Full 3.3V power supply

• -40°C to 85°C ambient operating temperature

• Lead-free (RoHS 6) packaging

Pin Assignment

• Web Servers and Exchange Servers

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55

GND

FSEL_A0

FSEL_B0

FSEL_C0

FSEL_D0

V_DD

IREF

OE_D

nQD1

QD1

nQD0

QD0

V_{DDO_D}

V_{DDO_C}

nQC1

QC1

nQC0

QC0

OE_C

V_DD

8XXXXXX

8413S12BI-126

FSEL_E0

V_DDA

XTAL_IN

XTAL_OUT

REF_SEL

GND

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

72-pin, 10mm x 10mm LQFP Package

January 7, 2016

12 3 4 5 6 7...30

中文翻译

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