Datasheet > 8413S12I-100_16

8413S12I-100_16

更新时间： 2024-11-05 01:07:35

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
33页	915K
描述
Clock Generator for Cavium Processors

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

8413S12I-100_16 数据手册

Clock Generator for Cavium

Processors

8413S12I-100

Data Sheet

General Description

Features

The 8413S12I-100 is a PLL-based clock generator specifically

designed for Cavium Networks Octeon II processors. This high

performance device is optimized to generate the processor core

reference clock, the PCI-Express reference clocks and the clocks for

both the Gigabit Ethernet MAC and PHY. The clock generator offers

ultra low-jitter, low-skew clock outputs, and edge rates that easily

meet the input requirements for the CN63XX and CN68XX series of

processors. The output frequencies are generated from a 25MHz

external input source or an external 25MHz parallel resonant crystal.

The industrial temperature range of the 8413S12I-100 supports

telecommunication, networking, and storage requirements.

• Ten 100MHz clocks for PCI Express, HCSL interface levels

• One single-ended QG LVCMOS/LVTTL clock output at 125MHz

• One single-ended QF LVCMOS/LVTTL clock output at 50MHz,

15 output impedance

• Two single-ended QREFx LVCMOS/LVTTL outputs at 25MHz,

15 output impedance

• Selectable external crystal or differential (single-ended) input

source

• Crystal oscillator interface designed for 25MHz, parallel resonant

crystal

• Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,

LVHSTL, HCSL input levels

Applications

• Systems using Cavium Processors

• CPE Gateway Design

• Home Media Servers

• 802.11n AP or Gateway

• Internal resistor bias on nCLK pin allows the user to drive CLK

input with external single-ended (LVCMOS/ LVTTL) input levels

• Supply Modes, (125MHz QG output and 25MHz QREFx outputs):

Core / Output

3.3V / 3.3V

3.3V / 2.5V

• Soho Secure Gateway

• Soho SME Gateway

• Supply Modes, (HCSL outputs, and 50MHz QF output):

• Wireless Soho and SME VPN Solutions

• Wired and Wireless Network Security

• Web Servers and Exchange Servers

Core / Output

3.3V / 3.3V

• -40°C to 85°C ambient operating temperature

• Available in Lead-free (RoHS 6) package

Pin Assignment

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55

GND

V_DDA

V_DD

IREF

OE_D

nQD1

QD1

nQD0

QD0

V_{DDO_D}

V_{DDO_C}

nQC1

QC1

nQC0

QC0

OE_C

V_DD

8XXXXXX

8413S12I-100

XTAL_IN

XTAL_OUT

REF_SEL

GND

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

72-pin, 10mm x 10mm LQFP Package

October 4, 2016

12 3 4 5 6 7...33

中文翻译

下载PDF

与8413S12I-100_16相关器件

型号	品牌	获取价格	描述	数据表
8413S12I-126	RENESAS	获取价格	HCSL/LVCMOS Clock Generator
84140	PSEMI	获取价格	Ultra-High Linearity Broadband Quad MOSFET Array
84140-00	PSEMI	获取价格	Ultra-High Linearity UltraCMOS Broadband Quad MOSFET Array
84140000	CRYDOM	获取价格	Trigger Output SSR,
84140-01	PSEMI	获取价格	Ultra-High Linearity UltraCMOS Broadband Quad MOSFET Array
84140010	CRYDOM	获取价格	Dual GN Series
84140-02	PSEMI	获取价格	Ultra-High Linearity UltraCMOS Broadband Quad MOSFET Array
841402DKILF	IDT	获取价格	Clock Generator, 400MHz, CMOS, 5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2/-4,
84140500	CRYDOM	获取价格	Trigger Output SSR,
84140510	CRYDOM	获取价格	Trigger Output SSR,

与8413S12I-100_16相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

13
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

7
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

34
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

30

产品中心

服务支持

精选活动

关于我们

帮助中心

8413S12I-100_16

8413S12I-100_16 数据手册

与8413S12I-100_16相关器件

与8413S12I-100_16相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

8413S12I-100_16

8413S12I-100_16 数据手册

与8413S12I-100_16相关器件

与8413S12I-100_16相关文章

您还可以找

您在本页遇到什么问题？