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8413S12B PDF预览

8413S12B

更新时间: 2024-12-02 01:10:47
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
33页 845K
描述
HCSL/ LVCMOS Clock Generator

8413S12B 数据手册

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HCSL/ LVCMOS Clock Generator  
8413S12B  
General Description  
Features  
The 8413S12B is a PLL-based clock generator. This high  
performance device is optimized to generate the processor core  
reference clock, the PCI-Express, sRIO, XAUI, SerDes reference  
clocks and the clocks for both the Gigabit Ethernet MAC and PHY.  
The clock generator offers ultra low-jitter, low-skew clock outputs.  
The output frequencies are generated from a 25MHz external input  
source or an external 25MHz parallel resonant crystal. The industrial  
temperature range of the 8413S12B supports telecommunication,  
networking, and storage requirements.  
Ten selectable 100MHz, 125MHz, 156.25MHz and 312.5MHz  
clocks for PCI Express, sRIO and GbE, HCSL interface levels  
One single-ended QG LVCMOS/LVTTL clock output at 125MHz  
One single-ended QF LVCMOS/LVTTL clock output at 50MHz,  
15output impedance  
Two single-ended QREFx LVCMOS/LVTTL outputs at 25MHz,  
15output impedance  
Selectable external crystal or differential (single-ended) input  
source  
Crystal oscillator interface designed for 25MHz, parallel resonant  
Applications  
crystal  
CPE Gateway Design  
Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,  
Home Media Servers  
LVHSTL, HCSL input levels  
802.11n AP or Gateway  
Soho Secure Gateway  
Internal resistor bias on nCLK pin allows the user to drive CLK  
input with external single-ended (LVCMOS/ LVTTL) input levels  
Supply Modes, (125MHz QG output and 25MHz QREFx outputs):  
Soho SME Gateway  
Wireless Soho and SME VPN Solutions  
Wired and Wireless Network Security  
Web Servers and Exchange Servers  
Core / Output  
3.3V / 3.3V  
3.3V / 2.5V  
Supply Modes, (HCSL outputs, and 50MHz QF output):  
Core / Output  
3.3V / 3.3V  
-40°C to 85°C ambient operating temperature  
Available in Lead-free (RoHS 6) package  
Pin Assignment  
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55  
1
2
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
nc  
VDD  
GND  
FSEL_A0  
FSEL_A1  
FSEL_B0  
FSEL_B1  
FSEL_C0  
FSEL_C1  
FSEL_D0  
FSEL_D1  
FSEL_E0  
VDDA  
FSEL_E1  
nc  
XTAL_IN  
XTAL_OUT  
nc  
3
IREF  
OE_D  
nQD1  
QD1  
nQD0  
QD0  
VDDO_D  
VDDO_C  
nQC1  
QC1  
nQC0  
QC0  
4
5
6
7
8
9
ꢇꢈꢅꢉ6ꢅꢁ  
10  
11  
12  
13  
14  
15  
16  
17  
18  
OE_C  
VDD  
GND  
nc  
REF_SEL  
GND  
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36  
ꢀꢁꢂSLQꢃꢄꢅꢆPPꢄ[ꢄꢅꢆPPꢄ/4)3ꢄ3DFNDJH  
©2016 Integrated Device Technology, Inc.  
1
Revision E, August 18, 2016  

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