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8413601SA PDF预览

8413601SA

更新时间: 2024-11-04 12:55:47
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
18页 831K
描述
OCTAL D-TYPE FLIP-FLOPS WITH CLEAR

8413601SA 技术参数

生命周期:Active零件包装代码:DFP
包装说明:DFP, FL20,.3针数:20
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:5.36
Is Samacsys:N系列:ALS
JESD-30 代码:R-GDFP-F20长度:13.09 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:30000000 Hz最大I(ol):0.024 A
位数:8功能数量:1
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装等效代码:FL20,.3封装形状:RECTANGULAR
封装形式:FLATPACK包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):29 mAProp。Delay @ Nom-Sup:20 ns
传播延迟(tpd):20 ns认证状态:Qualified
筛选级别:MIL-STD-883座面最大高度:2.45 mm
子类别:FF/Latch最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:MILITARY端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:6.92 mm最小 fmax:30 MHz
Base Number Matches:1

8413601SA 数据手册

 浏览型号8413601SA的Datasheet PDF文件第2页浏览型号8413601SA的Datasheet PDF文件第3页浏览型号8413601SA的Datasheet PDF文件第4页浏览型号8413601SA的Datasheet PDF文件第5页浏览型号8413601SA的Datasheet PDF文件第6页浏览型号8413601SA的Datasheet PDF文件第7页 
SN54ALS273, SN74ALS273  
OCTAL D-TYPE FLIP-FLOPS  
WITH CLEAR  
SDAS218A – APRIL 1982 – REVISED DECEMBER 1994  
SN54ALS273 . . . J PACKAGE  
SN74ALS273 . . . DW OR N PACKAGE  
(TOP VIEW)  
Contain Eight Flip-Flops With Single-Rail  
Outputs  
Buffered Clock and Direct-Clear Inputs  
Individual Data Input to Each Flip-Flop  
Applications Include:  
Buffer/Storage Registers  
Shift Registers  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
CLR  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
CLK  
Pattern Generators  
Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Standard Plastic (N)  
and Ceramic (J) 300-mil DIPs  
GND  
description  
SN54ALS273 . . . FK PACKAGE  
(TOP VIEW)  
These octal positive-edge-triggered flip-flops  
utilize TTL circuitry to implement D-type flip-flop  
logic with a direct-clear (CLR) input.  
Information at the data (D) inputs meeting the  
setup-time requirements is transferred to the  
Q outputs on the positive-going edge of the clock  
(CLK)pulse. Clocktriggeringoccursataparticular  
voltage level and is not directly related to the  
transition time of the positive-going pulse. When  
CLK is at either the high or low level, the D input  
signal has no effect at the output.  
3
2
1
20 19  
18  
4
5
6
7
8
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
6D  
17  
16  
15  
14  
9 10 11 12 13  
The SN54ALS273 is characterized for operation  
over the full military temperature range of 55°C  
to 125°C. The SN74ALS273 is characterized for  
operation from 0°C to 70°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
CLK  
D
X
H
L
CLR  
L
X
L
H
L
H
H
H
H or L  
X
Q
0
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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