HM-65262
16K x 1 Asynchronous
CMOS Static RAM
March 1997
Features
Description
• Fast Access Time. . . . . . . . . . . . . . . . . . . . 70/85nsMax The HM-65262 is a CMOS 16384 x 1-bit Static Random
Access Memory manufactured using the Intersil Advanced
SAJI V process. The device utilizes asynchronous circuit
design for fast cycle times and ease of use. The HM-65262
• Low Standby Current. . . . . . . . . . . . . . . . . . . .50µA Max
• Low Operating Current . . . . . . . . . . . . . . . . . 50mA Max
• Data Retention at 2.0V. . . . . . . . . . . . . . . . . . .20µA Max
• TTL Compatible Inputs and Outputs
• JEDEC Approved Pinout
is available in both JEDEC standard 20 pin, 0.300 inch wide
CERDIP and 20 pad CLCC packages, providing high board-
level packing density. Gated inputs lower standby current,
and also eliminate the need for pull-up or pull-down resis-
tors.
• No Clocks or Strobes Required
• Temperature Range . . . . . . . . . . . . . . . +55oC to +125oC
The HM-65262, a full CMOS RAM, utilizes an array of six
transistor (6T) memory cells for the most stable and lowest
possible standby supply current over the full military temper-
ature range. In addition to this, the high stability of the 6T
RAM cell provides excellent protection against soft errors
due to noise and alpha particles. This stability also improves
the radiation tolerance of the RAM over that of four transistor
(4T) devices.
• Equal Cycle and Access Time
• Single 5V Supply
• Gated Inputs-No Pull-Up or Pull-Down Resistors
Required
Ordering Information
(NOTE 1)
PACKAGE
CERDIP
TEMP. RANGE
70ns/20µA (NOTE 1) 85ns/20µA (NOTE 1)
85ns/400µA
PKG. NO.
o
o
-40 C to +85 C
HM1-65262B-9
29109BRA
HM1-65262-9
29103BRA
-
-
-
-
F20.3
F20.3
F20.3
J20.C
o
o
JAN #
SMD#
-55 C to +125 C
o
o
-55 C to +125 C
8413203RA
8413203YA
8413201RA
8413201YA
o
o
CLCC (SMD#)
NOTE:
-55 C to +125 C
1. Access Time/Data Retention Supply Current.
Pinouts
HM-65262 (CERDIP)
HM-65262 (CLCC)
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
9
V
20
19
A0
A1
A2
A3
A4
A5
A6
Q
CC
2
1 20 19
A0 - A13
Address Input
A13
18
A2
A3
A4
A5
A6
Q
A12
3
4
5
6
7
8
18 A12
17 A11
16 A10
15 A9
14 A8
13 A7
E
Q
D
Chip Enable/Power Down
Data Out
17 A11
A10
A9
16
15
14
13
Data In
A8
A7
V
/GND Ground
SS
9
10 11 12
V
Power (+5)
Write Enable
CC
12
D
W
GND 10
11 E
W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3002.2
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