System & DDR Clocks for Freescale
B4/T4 Processor Systems
840NT4
DATA SHEET
General Description
Features
The 840NT4 is a PLL-based clock generator designed to interface
with Freescale B4/T4 Processor systems. The clock generator offers
low jitter, low-skew clock outputs, frequency margining (0.025 -
0.312MHz step granularity), and spread spectrum clocking that
meets the ever-growing demands of Freescale’s next generation
processors.
• Ten LVCMOS clock outputs: four system clocks, four DDR clocks,
one RTC output, and one 25MHz reference clock
• Selectable input reference: crystal oscillator interface or
differential LVPECL input
• Output Frequency Range: 25MHz - 200MHz
• Serial Interface: I2C programmable
• Frequency Margining in <0.312MHz steps
• Spread spectrum for EMI reduction
• VCO range: 2GHz – 2.4GHz
• Voltage supply modes:
Core (VDD, VDDXTAL, VDDA) all core voltages must be identical
Output (VDDO_A,VDDO_B, VDDO_C, VDDO_REF0, VDDO_REF1
)
Core / Output
3.3V / 3.3V
3.3V / 2.5V
3.3V / 1.8V
2.5V / 2.5V
2.5V / 1.8V
• Output voltage levels are independently selectable
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
Output Frequency Reference Table
Pin Assignment
SYSCLK
DDRCLK
QC (MHz)
XTAL (MHz)
FSEL[3:0]
QA & QB (MHz)
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
66.67
66.67
66.67
66.67
100
66.67
100
36 35 34 33 32 31 30 29 28 27 26 25
FSEL3
FSEL2
FSEL1
FSEL0
GNDA
37
38
39
40
24
OE_C
125
23 GND_QB
133.33
66.67
100
QB2
QB1
22
21
41
42
43
44
45
46
20 QB0
100
VDDA
840NT4
19 VDDO_B
100
125
GND
18
17
16
15
VDDO_A
QA
100
133.33
66.67
100
VDD
125
MR
OE_A
OE_B
PLL_SEL
REF_SEL
GND_XTAL
125
47
48
1
14 GND_QA
REFOUT_SEL
125
125
13
2 3 4 5 6 7 8 9 10 11 12
125
133.33
66.67
100
133.33
133.33
133.33
133.33
125
133.33
840NT4
48-lead, 7.0mm x 7.0mm VFQFN
REVISION 1 6/16/14
1
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