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8404001CA PDF预览

8404001CA

更新时间: 2024-11-02 21:55:03
品牌 Logo 应用领域
德州仪器 - TI 栅极逻辑集成电路
页数 文件大小 规格书
13页 348K
描述
High Speed CMOS Logic 8-Input NAND Gate

8404001CA 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP-14针数:14
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:16 weeks
风险等级:1.97Is Samacsys:N
系列:HC/UHJESD-30 代码:R-GDIP-T14
长度:19.56 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE最大I(ol):0.004 A
功能数量:1输入次数:8
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V最大电源电流(ICC):0.04 mA
Prop。Delay @ Nom-Sup:30 ns传播延迟(tpd):195 ns
认证状态:Qualified施密特触发器:NO
筛选级别:MIL-STD-883座面最大高度:5.08 mm
子类别:Gate最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.67 mm
Base Number Matches:1

8404001CA 数据手册

 浏览型号8404001CA的Datasheet PDF文件第2页浏览型号8404001CA的Datasheet PDF文件第3页浏览型号8404001CA的Datasheet PDF文件第4页浏览型号8404001CA的Datasheet PDF文件第5页浏览型号8404001CA的Datasheet PDF文件第6页浏览型号8404001CA的Datasheet PDF文件第7页 
CD54/74HC30,  
CD54/74HCT30  
Data sheet acquired from Harris Semiconductor  
SCHS121D  
High Speed CMOS Logic  
8-Input NAND Gate  
August 1997 - Revised September 2003  
Features  
Description  
• Buffered Inputs  
The ’HC30 and ’HCT30 each contain an 8-input NAND gate  
in one package. They provide the system designer with the  
direct implementation of the positive logic 8-input NAND  
function. Logic gates utilize silicon gate CMOS technology to  
achieve operating speeds similar to LSTTL gates with the  
low power consumption of standard CMOS integrated cir-  
cuits. All devices have the ability to drive 10 LSTTL loads.  
The HCT logic family is functionally pin compatible with the  
• Typical Propagation Delay: 10ns at V  
o
= 5V,  
[ /Title  
(CD54H  
C30,  
CD74H  
C30,  
CC  
C = 15pF, T = 25 C  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C standard LS logic family.  
CD74H  
CT30)  
/Subject  
(High  
Speed  
CMOS  
Logic 8-  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
TEMP. RANGE  
o
PART NUMBER  
CD54HC30F3A  
CD54HCT30F3A  
CD74HC30E  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld CERDIP  
14 Ld PDIP  
• HC Types  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
• HCT Types  
CD74HC30M  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOP  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
CD74HC30MT  
CD74HC30M96  
CD74HC30NSR  
CD74HC30PW  
CD74HC30PWR  
CD74HC30PWT  
CD74HCT30E  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
l
OL OH  
14 Ld TSSOP  
14 Ld TSSOP  
14 Ld TSSOP  
14 Ld PDIP  
Pinout  
CD54HC30, CD54HCT30 (CERDIP)  
CD74HC30 (PDIP, SOIC, SOP, TSSOP)  
CD74HCT30 (PDIP, SOIC)  
TOP VIEW  
A
B
1
2
3
4
5
6
7
14  
V
CD74HCT30M  
CD74HCT30MT  
CD74HCT30M96  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
CC  
13 NC  
C
12  
11  
H
G
D
E
10 NC  
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
F
9
8
NC  
Y
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated.  
1

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