Datasheet > 831724

831724

更新时间： 2024-11-05 01:13:47

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
22页	496K
描述
Differential Clock/Data Multiplexer

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831724 数据手册

Differential Clock/Data Multiplexer

831724

Datasheet

General Description

Features

• 2:1 differential clock/data multiplexer with fanout

• Two selectable, differential inputs

The 831724 is a high-performance, differential HCSL clock/data

multiplexer and fanout buffer. The device is designed for the

multiplexing and fanout of high-frequency clock and data signals.

The device has two differential, selectable clock/data inputs. The

selected input signal is distributed to four low-skew differential HCSL

outputs. Each input pair accepts HCSL, LVDS and LVPECL levels.

The 831724 is characterized to operate from a 3.3V power supply.

Guaranteed input, output-to-output and part-to-part skew

characteristics make the 831724 ideal for those clock and data

distribution applications demanding well-defined performance and

repeatability. The 831724 supports the clock multiplexing and

distribution of PCI Express Generation 1, 2, and 3 clock signals.

• Each differential input pair can accept the following levels: HCSL,

LVDS, LVPECL.

• Four differential HCSL outputs

• Maximum input/output clock frequency: 350MHz

• Maximum input/output data rate: 700Mb/s (NRZ)

• LVCMOS interface levels for all control inputs

• PCI Express Gen 1,2,3 jitter compliant

• Input skew: 165ps (maximum)

• Output skew: 175ps (maximum)

• Part-to-part skew: 450ps (maximum)

• Full 3.3V supply voltage

• Available in lead-free (RoHS 6) package

• -40°C to 85°C ambient operating temperature

Pin Assignment

Block Diagram

32 31 30 29 28 27 26 25

nQA

IREF

VDD

nOED

CLK0

nQB

Pulldown

nOEC

Pullup/down

22 nc

CLK0

nCLK0

CLK1

Pulldown

nQC

nCLK0

Pullup/down

nCLK1

nQD

SEL

nOEA

V^DD

CLK1

Pulldown

nCLK1

10 11 12 13 14 15 16

Pullup

831724I

32-Lead VFQFN

5mm x 5mm x 0.925mm package body

SEL

K Package

Top View

Revision B November 16, 2016

12 3 4 5 6 7...22

中文翻译

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