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8305AGIL PDF预览

8305AGIL

更新时间: 2024-02-10 05:29:54
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
15页 209K
描述
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER

8305AGIL 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:4.40 X 3 MM, 0.925 MM HEIGHT, MO-153, TSSOP-16针数:16
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.08
系列:8305输入调节:DIFFERENTIAL MUX
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:5 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:16
实输出次数:4最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):225电源:3.3 V
Prop。Delay @ Nom-Sup:4 ns传播延迟(tpd):4 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.035 ns
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mm最小 fmax:350 MHz
Base Number Matches:1

8305AGIL 数据手册

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ICS8305I  
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/  
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
The ICS8305I is a low skew, 1-to-4, Differential/ • 4 LVCMOS/LVTTL outputs  
ICS  
LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a  
• Selectable differential or LVCMOS/LVTTL clock inputs  
HiPerClockS™  
member of the HiPerClockS™ family of High  
Performance Clock Solutions from ICS. The  
ICS8305I has selectable clock inputs that accept  
CLK, nCLK pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL  
either differential or single ended input levels.The clock enable is  
internally synchronized to eliminate runt pulses on the outputs  
during asynchronous assertion/deassertion of the clock enable  
pin. Outputs are forced LOW when the clock is disabled. A sepa-  
rate output enable pin controls whether the outputs are in the  
active or high impedance state.  
LVCMOS_CLK supports the following input types:  
LVCMOS, LVTTL  
• Maximum output frequency: 350MHz  
• Output skew: 40ps (maximum)  
• Part-to-part skew: 700ps (maximum)  
Additive phase jitter, RMS: 0.04ps (typical)  
• 3.3V core, 3.3V, 2.5V or 1.8V output operating supply  
• -40°C to 85°C ambient operating temperature  
• Lead-Free package fully RoHS compliant  
Guaranteed output and part-to-part skew characteristics make  
the ICS8305I ideal for those applications demanding well de-  
fined performance and repeatability.  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
1
2
3
4
5
6
7
8
GND  
OE  
VDD  
16  
15  
14  
13  
12  
11  
10  
9
Q0  
VDDO  
Q1  
GND  
Q2  
VDDO  
Q3  
CLK_EN  
D
Q
LE  
CLK_EN  
CLK  
nCLK  
CLK_SEL  
LVCMOS_CLK  
LVCMOS_CLK  
0
Q0  
Q1  
Q2  
Q3  
CLK  
nCLK  
1
GND  
CLK_SEL  
ICS8305I  
16-LeadTSSOP  
4.4mm x 3.0mm x 0.92mm package body  
G Package  
Top View  
OE  
8305AGI  
www.icst.com/products/hiperclocks.html  
REV. B MAY 19, 2005  
1

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