82V3002APVG

更新时间： 2024-02-09 09:27:31

品牌	Logo	应用领域
艾迪悌 - IDT		电信集成电路电信电路光电二极管输入元件 PC
页数	文件大小	规格书
29页	426K
描述
WAN PLL WITH DUAL REFERENCE INPUTS

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82V3002APVG 技术参数

是否Rohs认证：	不符合	生命周期：	Active
Reach Compliance Code：	not_compliant	风险等级：	5.88
JESD-30 代码：	R-PDSO-G56	JESD-609代码：	e0
湿度敏感等级：	1	端子数量：	56
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装等效代码：	SSOP56,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	电源：	3.3 V
认证状态：	Not Qualified	子类别：	Clock Generators
最大压摆率：	50 mA	标称供电电压：	3.3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
Base Number Matches：	1

82V3002APVG 数据手册

WAN PLL WITH DUAL

REFERENCE INPUTS

IDT82V3002A

FEATURES

•

Holdover frequency accuracy of 0.025 ppm

Phase slope of 5 ns/125 µs

Attenuates wander from 2.1 Hz

Fast Lock mode

Provides Time Interval Error (TIE) correction

MTIE of 600 ns

JTAG boundary scan

Holdover status indication

Freerun status indication

Normal status indication

•

Supports AT&T TR62411 and Telcordia GR-1244-CORE Stra-

tum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1

interfaces

•

Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s inter-

faces

Supports ITU-T G.812 Type IV clocks for 1544 kbit/s interface

and 2048 kbit/s interfaces

Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 tim-

ing for E1 interface

Selectable input reference signal: 8 kHz, 1.544 MHz or 2.048

MHz

Lock status indication

Input primary reference quality indication

3.3 V operation with 5 V tolerant I/O

Package available: 56-pin SSOP (Green option available)

•

Accepts reference inputs from two independent sources

Provides eight types of clock signals: C1.5o, C3o, C2o, C4o,

C6o, C8o, C16o and C32o

•

Provides six types of 8 kHz framing pulses: F0o, F8o, F16o,

F32o, RSP and TSP

DESCRIPTION

The IDT82V3002A is a WAN PLL with dual reference inputs. It

contains a Digital Phase-Locked Loop (DPLL), which generates ST-BUS

clocks and framing signals that are phase locked to a 2.048 MHz, 1.544

MHz or 8 kHz input reference.

The IDT82V3002A provides eight types of clock signals (C1.5o, C3o,

C6o, C2o, C4o, C8o, C16o, C32o) and six types of framing signals (F0o,

F8o, F16o, F32o, RSP, TSP) for the multitrunk T1 and E1 primary rate

transmission links.

Type IV clocks for 1544 kbit/s interface and 2048 kbit/s interface. It meets

the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander,

frequency accuracy, capture range, phase change slope, holdover

frequency accuracy and MTIE (Maximum Time Interval Error)

requirements for these specifications.

The IDT82V3002A can be used in synchronization and timing control

for T1 and E1 systems, or used as ST-BUS clock and frame pulse

sources. It can also be used in access switch, access routers, ATM edge

switches, wireless base station controllers, or IADs (Integrated Access

Devices), PBXs and line cards.

The IDT82V3002A is compliant with AT&T TR62411, Telcordia GR-

1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4, ETSI ETS

300 011, ITU-T G.813 Option 1 for 2048 kbit/s interface, and ITU-T G.812

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.

October 15, 2008

DSC-6243/4

2006 Integrated Device Technology, Inc.

12 3 4 5 6 7...29

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