QUAD NON-PROGRAMMABLE
PCM CODEC
821004J
DESCRIPTION
FEATURES
· 4 channel CODEC with on-chip digital filters
· Selectable A-law or m-law companding
· Master clock frequency selection: 2.048 MHz, 4.096 MHz or
8.192 MHz
The 821004J is a single-chip, four channel PCM CODEC with on-chip
filters. The device provides analog-to-digital and digital-to-analog
conversions and supports both a-law and m- law companding. The digital
filters in 821004J provides the necessary transmit and receive filtering for
voice telephone circuit to interface with time-division multiplexed systems.
All of the digital filters are performed in digital signal processors operating
from an internal clock, which is derived from MCLK. The fixed filters set
the transmit and receive gain and frequency response.
- Internal timing automatically adjusted based on MCLK and frame
sync signal
· Separate PCM and master clocks
· Single PCM port with up to 8.192 MHz data rate (128 time slots)
· Transhybrid balance impedance hardware adjustable via external
components
· Transmit gains hardware adjustable via external components
· Low power +5.0 V CMOS technology
· +5.0 V single power supply
In the 821004J the PCM data is transmitted to and received from the
PCM highway in time slots determined by the individual Frame Sync signals
(FSRn and FSXn, where n = 1-4) at rates from 256 KHz to 8.192 MHz. Both
Long and Short Frame Sync modes are available in the 821004J.
The 821004J can be used in digital telecommunication applications
such as PBX, Central Office Switch, Digital Telephone and Integrated Voice/
Data Access Unit.
· Package available: 32 pin PLCC
FUNCTIONAL BLOCK DIAGRAM
Anolog Front End
CH1
IIN1
FSX1
PCM TSA 1
FSR1
VOUT1
FSX2
PCM TSA 2
FSR2
Anolog Front End
CH2
IIN2
FSX3
VOUT2
PCM TSA 3
FSR3
DSP
FSX4
FSR4
DX
PCM TSA 4
Anolog Front End
CH3
IIN3
VOUT3
TSC
DR
PCM Interface
Anolog Front End
CH4
IIN4
VOUT4
PCLK
MCLK
Clock
PDN 1~ 4
&
Control
IREF
CNF
A/m
Reference Circuits
NOVEMBER 2020
INDUSTRIAL TEMPERATURE RANGE
1
DSC-6807/1