Datasheet > 814252CKI-02LFT

814252CKI-02LFT

更新时间： 2024-09-24 19:13:07

品牌	Logo	应用领域
艾迪悌 - IDT		时钟外围集成电路晶体
页数	文件大小	规格书
18页	346K
描述
Clock Generator, 312.5MHz, 5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32

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814252CKI-02LFT 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	VQCCN,	针数：	32
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.22
JESD-30 代码：	S-XQCC-N32	JESD-609代码：	e3
长度：	5 mm	端子数量：	32
最高工作温度：	85 °C	最低工作温度：	-40 °C
最大输出时钟频率：	312.5 MHz	封装主体材料：	UNSPECIFIED
封装代码：	VQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
主时钟/晶体标称频率：	25 MHz	认证状态：	Not Qualified
座面最大高度：	1 mm	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	5 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

814252CKI-02LFT 数据手册

PRELIMINARY

VCXO JITTER ATTENUATOR &

FEMTOCLOCK™ MULTIPLIER

ICS814252I-02

GENERAL DESCRIPTION

FEATURES

The ICS814252I-02 is

member of the

• Two LVDS outputs

ICS

HiperClockS™ family of high performance clock

solutions from IDT. The ICS814252I-02 is a PLL

based synchronous multiplier that is optimized for

PDH or SONET to Ethernet clock jitter attenuation

Each output supports independent frequency selection at

25MHz, 125MHz, 156.25MHz and 312.5MHz

HiPerClockS™

• Two differential inputs support the following input types:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

and frequency translation. The device contains two internal

frequency multiplication stages that are cascaded in series.

The first stage is a VCXO PLL that is optimized to provide

reference clock jitter attenuation. The second stage is a

FemtoClock™ frequency multiplier that provides the low jitter,

high frequency Ethernet output clock that easily meets Gigabit

and 10 Gigabit Ethernet jitter requirements. Pre-divider and

output divider multiplication ratios are selected using device

selection control pins. The multiplication ratios are optimized

to support most common clock rates used in PDH, SONET

and Ethernet applications. The VCXO requires the use of an

external, inexpensive pullable crystal. The VCXO uses external

passive loop filter components which allows configuration of

the PLL loop bandwidth and damping characteristics. The

device is packaged in a space-saving 32-VFQFN package and

supports industrial temperature range.

• Accepts input frequencies from 8kHz to 155.52MHz including

8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,

125MHz and 155.52MHz

• Attenuates the phase jitter of the input clock by using a low-

cost pullable fundamental mode VCXO crystal

• VCXO PLL bandwidth can be optimized for jitter attenuation

and reference tracking using external loop filter connection

• FemtoClock frequency multiplier provides low jitter, high

frequency output

• Absolute pull range: 50ppm

• FemtoClock VCO frequency: 625MHz

• RMS phase jitter @ 125MHz, using a 25MHz crystal

(10kHz – 20MHz): 1.2ps (typical)

• 3.3V supply voltage

• -40°C to 85°C ambient operating temperature

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

PIN ASSIGNMENT

32 31 30 29 28 27 26 25

LF1

LF0

GND

nQB

ISET

GND

V^DDO

nQA

ICS814252I-02

CLK_SEL

V^DD

RESERVED

GND

ODASEL_0

9 10 11 12 13 14 15 16

32-Lead VFQFN

5mm x 5mm x 0.925 package body

K Package

Top View

The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization

and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.

IDT^™/ ICS^™VCXO JITTER ATTENUATOR/MULTIPLIER

ICS814252CKI-02 REV. A OCTOBER 5, 2007

12 3 4 5 6 7...18

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