Datasheet > 80HCPS1848

80HCPS1848

更新时间： 2024-09-14 14:57:39

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
85页	1580K
描述
RapidIO Switch

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数据手册

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80HCPS1848 数据手册

18-Port, 48-Lane, 240Gbps,

Gen2 RapidIO Switch

CPS-1848

Datasheet

Description

Features

•

RapidIO ports

The CPS-1848 (80HCPS1848) is a RapidIO Specification (Rev. 2.1)

compliant Secure Packet Switch whose functionality is central to

routing packets for distribution among DSPs, processors, FPGAs,

other switches, or any other RapidIO-based devices. It can also be

used in RapidIO backplane switching. The CPS-1848 supports Serial

RapidIO (S-RIO) packet switching (unicast, multicast, and an optional

broadcast) from any of its 18 input ports to any of its 18 output ports.

— 48 bidirectional S-RIO lanes

— Port widths of 1x, 2x, and 4x allow up to 20 Gbps per port

— Port speeds selectable: 6.25, 5, 3.125, 2.5, or 1.25 Gbaud

— Support Level I defined short or long haul reach, and Level II

defined short-, medium-, or long-run reach for each PHY speed

— Error Management Extensions support

— Software-assisted error recovery, supporting hot swap

Block Diagram

•

I C Interfaces

— Provides I C port for maintenance and error reporting

Quadrant 0

Lanes 0-3, 16-19, 32-35

Quadrant 3

Lanes 12-15, 28-31, 44-47

— Master or Slave operation

— Master allows power-on configuration from external ROM

Ports 0, 4, 8, 12, 16

Ports 3, 7, 11, 15

— Master mode configuration with external image compressing and

checksum

Switch

CPS-1848

RapidIO Gen2

Switch Fabric

— 240 Gbps peak throughput

— Non-blocking data flow architecture

— Configurable for Cut-Through or Store-and-Forward data flow

— Very low latency for all packet lengths and load conditions

— Internal queuing buffer and retransmit buffer

— Standard transmitter- or receiver-controlled flow control

— Global routing or Local Port routing capability

— Supports up to 40 simultaneous multicast masks, with broadcast

Event Management and Maintenance

Registers

I²C Controller

Ports 1, 5, 9, 13, 17

JTAG Controller

Ports 2, 6, 10, 14

Lanes 8-11, 24-27, 40-43

Quadrant 2

Lanes 4-7, 20-23, 36-39

— Performance monitoring counters for performance and

diagnostics analysis. Per input port and output port counters

Quadrant 1

•

SerDes

— Transmitter pre-emphasis and drive strength + receiver

equalization provides best possible signal integrity

Typical Applications

— Embedded PRBS generation and detection with programmable

polynomials support Bit Error Rate testing

•

High-performance computing

Wireless

Additional Information

Defense and aerospace

Video and imaging

— Packet Trace/Mirror. Each input port can copy all incoming

packets matching user-defined criteria to a “trace” output port.

— Packet Filter. Each input port can filter (drop) all incoming packets

matching user-defined criteria.

— Device configurable through any of S-RIO ports, I C, or JTAG

— Full JTAG Boundary Scan Support (IEEE1149.1 and 1149.6)

— Lidless 784-FCBGA Package: 29  29 mm, 1.0 mm ball pitch

March 15, 2019

12 3 4 5 6 7...85

中文翻译

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