C8051F330/1/2/3/4/5
Mixed Signal ISP Flash MCU Family
High Speed 8051 µC Core
Analog Peripherals
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10-Bit ADC (‘F330/2/4 only)
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Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
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Up to 200 ksps
Up to 16 external single-ended or differential inputs
VREF from internal VREF, external pin or VDD
Internal or external start of conversion source
Built-in temperature sensor
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Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler
Memory
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768 bytes internal data RAM (256 + 512)
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8 kB (‘F330/1), 4 kB (‘F332/3), or 2 kB (‘F334/5)
Flash; In-system programmable in 512-byte Sec-
tors—512 bytes are reserved in the 8 kB devices
Digital Peripherals
On-Chip Debug
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17 Port I/O; All 5 V tolerant with high sink current
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On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
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Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports
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Four general purpose 16-bit counter/timers
16-Bit programmable counter array (PCA) with three
capture/compare modules
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Real time clock mode using PCA or timer and exter-
nal clock source
Low cost, complete development kit
Supply Voltage 2.7 to 3.6 V
Clock Sources
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Typical operating current: 6.4 mA at 25 MHz;
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Two internal oscillators:
9 µA at 32 kHz
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24.5 MHz with ±2% accuracy supports crystal-less
UART operation
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Typical stop mode current: 0.1 µA
Temperature Range: –40 to +85 °C
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80/40/20/10 kHz low frequency, low power
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External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
Can switch between clock sources on-the-fly; useful
in power saving modes
20-Pin QFN or 20-pin PDIP
ANALOG
PERIPHERALS
DIGITAL I/O
UART
Port 0
SMBus
10-bit
Current
DAC
A
M
U
X
10-bit
200 ksps
ADC
SPI
PCA
Port 1
P2.0
‘F330 only
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Timer 0
Timer 1
Timer 2
Timer 3
TEMP
SENSOR
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VOLTAGE
COMPARATOR
‘F330/2/4 only
24.5 MHz PRECISION
INTERNAL OSCILLATOR
LOW FREQUENCY INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
2/4/8 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
768 B SRAM
POR WDT
CIRCUITRY
Rev. 1.4 7/05
Copyright © 2005 by Silicon Laboratories
C8051F33x
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.