Datasheet > 7C142-25

7C142-25

更新时间： 2024-11-25 22:22:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
18页	341K
描述
2Kx8 Dual-Port Static RAM

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中文翻译

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数据手册

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7C142-25 数据手册

1CY7C132/CY7C136

fax id: 5201

CY7C132/CY7C136

CY7C142/CY7C146

2Kx8 Dual-Port Static RAM

Features

Functional Description

• True Dual-Ported memory cells which allow simulta-

neous reads of the same memory location

• 2K x 8 organization

• 0.65-micron CMOS for optimum speed/power

• High-speed access: 15 ns

The CY7C132/CY7C136/CY7C142 and CY7C146 are

high-speed CMOS 2K by 8 dual-port static RAMs. Two ports

are provided to permit independent access to any location in

memory. The CY7C132/ CY7C136 can be utilized as either a

standalone 8-bit dual-port static RAM or as a MASTER du-

al-port RAM in conjunction with the CY7C142/CY7C146

SLAVE dual-port device in systems requiring 16-bit or greater

word widths. It is the solution to applications requiring shared

or buffered data such as cache memory for DSP, bit-slice, or

multiprocessor designs.

• Low operating power: I = 90 mA (max.)

• Fully asynchronous operation

• Automatic power-down

• Master CY7C132/CY7C136 easily expands data bus

width to 16 or more bits using slave CY7C142/CY7C146

• BUSY output flag on CY7C132/CY7C136; BUSY input

on CY7C142/CY7C146

• INT flag for port-to-port communication (52-pin

PLCC/PQFP versions)

• Availablein 48-pin DIP (CY7C132/142), 52-pin PLCCand

52-pin TQFP (CY7C136/146)

• Pin-compatible and functionally equivalent to

IDT7132/IDT7142

Each port has independent control pins; chip enable (CE),

write enable (R/W), and output enable (OE). BUSY flags are

provided on each port. In addition, an interrupt flag (INT) is

provided on each port of the 52-pin PLCC version. BUSY sig-

nals that the port is trying to access the same location currently

being accessed by the other port. On the PLCC version, INT

is an interrupt flag indicating that data has been placed in a

unique location (7FF for the left port and 7FE for the right port).

An automatic power-down feature is controlled independently

on each port by the chip enable (CE) pins.

The CY7C132/CY7C142 are available in 48-pin DIP. The

CY7C136/CY7C146 are available in 52-pin PLCC and PQFP.

Logic Block Diagram

Pin Configuration

R/W

DIP

Top View

R/W

BUSY

R/W

BUSY

10L

I/O

10R

I/O

CONTROL

I/O

CONTROL

[1]

BUSY

10L

10R

MEMORY

ARRAY

ADDRESS

DECODER

ADDRESS

DECODER

7C132

13 7C142

I/O

ARBITRATION

LOGIC

(7C132/7C136 ONLY)

AND

INTERRUPTLOGIC

(7C136/7C146 ONLY)

I/O

R/W

I/O

GND

[2]

INT

C132-2

C132-1

Notes:

1. CY7C132/CY7C136 (Master): BUSY is open drain output and requires pull-up resistor.

CY7C142/CY7C146 (Slave): BUSY is input.

2. Open drain outputs; pull-up resistor required.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

December 1989 – Revised March 27, 1997

12 3 4 5 6 7...18

中文翻译

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与7C142-25相关器件

型号	品牌	获取价格	描述	数据表
7C142-30	CYPRESS	获取价格	2Kx8 Dual-Port Static RAM
7C142-35	CYPRESS	获取价格	2Kx8 Dual-Port Static RAM
7C142-45	CYPRESS	获取价格	2Kx8 Dual-Port Static RAM
7C142-55	CYPRESS	获取价格	2Kx8 Dual-Port Static RAM
7C-1431818MAB-B	ETC	获取价格	OSCILLATOR Part Numbering System - CMOS
7C1431818MAB-B	ETC	获取价格	OSCILLATOR Part Numbering System - CMOS
7C-1431818MAB-T	ETC	获取价格	OSCILLATOR Part Numbering System - CMOS
7C1431818MAB-T	ETC	获取价格	OSCILLATOR Part Numbering System - CMOS
7C-1431818MAC-B	ETC	获取价格	OSCILLATOR Part Numbering System - CMOS
7C1431818MAC-B	ETC	获取价格	OSCILLATOR Part Numbering System - CMOS

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