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74VHCT541AMT PDF预览

74VHCT541AMT

更新时间: 2024-11-29 13:04:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输出元件
页数 文件大小 规格书
8页 66K
描述
AHCT/VHCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, SOP-20

74VHCT541AMT 技术参数

生命周期:Active包装说明:SOP,
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.57系列:AHCT/VHCT
JESD-30 代码:R-PDSO-G20长度:12.8 mm
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):9.5 ns
座面最大高度:2.65 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:7.5 mmBase Number Matches:1

74VHCT541AMT 数据手册

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74VHCT541A  
OCTAL BUS BUFFER  
WITH 3 STATE OUTPUTS (NON INVERTED)  
HIGH SPEED:tPD =3.6ns (TYP.) atVCC = 5V  
LOW POWER DISSIPATION:  
CC =4 µA (MAX.) at TA =25 oC  
I
COMPATIBLEWITH TTL OUTPUTS:  
VIH =2V (MIN), VIL = 0.8V(MAX)  
POWERDOWN PROTECTIONON INPUTS&  
OUTPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 8 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
OPERATING VOLTAGERANGE:  
M
T
(Micro Package)  
(TSSOPPackage)  
ORDER CODES :  
74VHCT541AM  
74VHCT41AT  
input AND such that if either G1 and G2 are high,  
all eight outputs are in the high impedance state.  
In order to enhance PC board layout, the AC541  
offers a pinout having inputs and outputs on  
opposite sidesof the package.  
Power down protection is provided on all inputs  
and outputs and 0 to 7V can be accepted on  
inputs with no regard to the supply voltage. This  
device can be used to interface 5V to 3V.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
VCC (OPR)= 4.5V to 5.5V  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES541  
IMPROVED LATCH-UP IMMUNITY  
LOWNOISE:VOLP = 0.9V(Max.)  
DESCRIPTION  
The VHCT541A is an advanced high speed  
CMOS OCTAL BUS BUFFER (3-STATE)  
fabricated with sub-micron silicon gate and  
double-layermetal wiring C2MOS technology.  
The 3 STATE control gate operates as a two  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/8  
August 1999  

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