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74VHCT05AMTR PDF预览

74VHCT05AMTR

更新时间: 2024-11-04 22:56:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 151K
描述
HEX INVERTER (OPEN DRAIN)

74VHCT05AMTR 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP-14
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.83
Is Samacsys:N系列:AHCT/VHCT
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:INVERTER最大I(ol):0.008 A
湿度敏感等级:1功能数量:6
输入次数:1端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:OPEN-DRAIN封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:5 V
Prop。Delay @ Nom-Sup:11.3 ns传播延迟(tpd):11.3 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
Base Number Matches:1

74VHCT05AMTR 数据手册

 浏览型号74VHCT05AMTR的Datasheet PDF文件第2页浏览型号74VHCT05AMTR的Datasheet PDF文件第3页浏览型号74VHCT05AMTR的Datasheet PDF文件第4页浏览型号74VHCT05AMTR的Datasheet PDF文件第5页浏览型号74VHCT05AMTR的Datasheet PDF文件第6页浏览型号74VHCT05AMTR的Datasheet PDF文件第7页 
74VHCT05A  
HEX INVERTER (OPEN DRAIN)  
HIGH SPEED: t = 3.5 ns (TYP.) at V = 5V  
PZ CC  
LOW POWER DISSIPATION:  
I
= 2 µA (MAX.) at T =25°C  
CC  
A
COMPATIBLE WITH TTL OUTPUTS:  
= 2V (MIN.), V = 0.8V (MAX)  
V
IH  
IL  
POWER DOWN PROTECTION ON INPUTS  
OPERATING VOLTAGE RANGE:  
SOP  
TSSOP  
V
(OPR) = 4.5V to 5.5V  
CC  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 05  
ORDER CODES  
PACKAGE  
IMPROVED LATCH-UP IMMUNITY  
TUBE  
T & R  
LOW NOISE: V  
= 0.8V (MAX.)  
OLP  
SOP  
74VHCT05AM 74VHCT05AMTR  
74VHCT05ATTR  
TSSOP  
DESCRIPTION  
The 74VHCT05A is an advanced high-speed  
CMOS OPEN DRAIN HEX INVERTER fabricated  
with sub-micron silicon gate and double-layer  
regard to the supply voltage. This device can be  
used to interface 5V to 3V since all inputs are  
equipped with TTL threshold.  
2
metal wiring C MOS technology.  
The internal circuit is composed of 3 stages  
including buffer output, which provides high noise  
immunity and stable output.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
June 2001  
1/8  

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