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74VHCT04AT PDF预览

74VHCT04AT

更新时间: 2024-11-04 22:56:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 55K
描述
HEX INVERTER

74VHCT04AT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-14针数:14
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.13Is Samacsys:N
系列:AHCT/VHCTJESD-30 代码:R-PDSO-G14
JESD-609代码:e0长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:INVERTER
最大I(ol):0.008 A功能数量:6
输入次数:1端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:8.5 ns
传播延迟(tpd):8.5 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.2 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

74VHCT04AT 数据手册

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74VHCT04A  
HEX INVERTER  
HIGH SPEED:tPD =4.7ns (TYP.) atVCC = 5V  
LOW POWER DISSIPATION:  
I
CC =2 µA (MAX.) at TA =25 oC  
COMPATIBLEWITH TTL OUTPUTS:  
VIH =2V (MIN), VIL = 0.8V(MAX)  
POWERDOWN PROTECTIONON INPUTS&  
OUTPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 8 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
OPERATING VOLTAGERANGE:  
M
T
(Micro Package)  
(TSSOPPackage)  
ORDER CODES :  
74VHCT04AM  
74VHCT04AT  
The internal circuit is composed of 3 stages  
including buffer output, which provide high noise  
immunity and stable output.  
Power down protection is provided on all inputs  
and outputs and 0 to 7V can be accepted on  
inputs with no regard to the supply voltage. This  
device can be used to interface 5V to 3V.  
VCC (OPR)= 4.5V to 5.5V  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES04  
IMPROVED LATCH-UP IMMUNITY  
LOWNOISE:VOLP = 0.8V(Max.)  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74VHCT04A is an advanced high-speed  
CMOS HEX INVERTER fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C2MOS technology.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/7  
August 1999  

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