July 1997
Revised February 2005
74VHCT00A
Quad 2-Input NAND Gate
General Description
Features
The VHCT00A is an advanced high-speed CMOS 2-Input
NAND Gate fabricated with silicon gate CMOS technology.
It achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. The internal circuit is composed of 3
stages, including buffer output, which provide high noise
immunity and stable output.
■ High speed: tPD 5.0 ns (typ) at TA 25 C
■ High noise immunity: VIH 2.0V, VIL 0.8V
■ Power down protection is provided on all inputs and
outputs
■ Low noise: VOLP 0.8V (max)
■ Low power dissipation:
Protection circuits ensure that 0V to 7V can be applied to
the input pins without regard to the supply voltage and to
ICC
2 A (max) at TA 25 C
■ Pin and function compatible with 74HCT00
the output pins with VCC
0V. These circuits prevent
device destruction due to mismatched supply and input/
output voltages. This device can be used to interface 3V to
5V systems and two supply systems such as battery
backup.
Ordering Code:
Package
Order Number
Package Description
Number
74VHCT00AM
74VHCT00ASJ
74VHCT00AMTC
M14A
M14D
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MTC14
MTC14
74VHCT00AMTCX_NL
(Note 1)
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74VHCT00AN
N14A
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74VHCT00AN_NL
(Note 1)
Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Use this number to order device.
© 2005 Fairchild Semiconductor Corporation
DS500023
www.fairchildsemi.com