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74VHC86MTR

更新时间： 2024-11-21 04:48:03

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
11页	234K
描述
QUAD EXCLUSIVE OR GATE

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中文翻译

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数据手册

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74VHC86MTR 数据手册

74VHC86

QUAD EXCLUSIVE OR GATE

■

HIGH SPEED: t = 4.8 ns (TYP.) at V = 5V

PD CC

LOW POWER DISSIPATION:

= 2 µA (MAX.) at T =25°C

■

HIGH NOISE IMMUNITY:

= V = 28% V (MIN.)

NIH

NIL

■

POWER DOWN PROTECTION ON INPUTS

SYMMETRICAL OUTPUT IMPEDANCE:

SOP

TSSOP

|I | = I = 8 mA (MIN)

Table 1: Order Codes

PACKAGE

■

BALANCED PROPAGATION DELAYS:

PLH

PHL

T & R

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 5.5V

SOP

74VHC86MTR

74VHC86TTR

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 86

TSSOP

■

IMPROVED LATCH-UP IMMUNITY

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

LOW NOISE: V

= 0.8V (MAX.)

OLP

DESCRIPTION

The 74VHC86 is an advanced high-speed CMOS

QUAD EXCLUSIVE OR GATE fabricated with

sub-micron silicon gate and double-layer metal

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

wiring C MOS technology.

Figure 1: Pin Connection And IEC Logic Symbols

Rev. 5

1/11

November 2004

12 3 4 5 6 7...11

中文翻译

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