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74VHC86MTC_08 PDF预览

74VHC86MTC_08

更新时间: 2024-09-15 12:51:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
10页 298K
描述
Quad 2-Input Exclusive-OR Gate

74VHC86MTC_08 数据手册

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February 2008  
74VHC86  
Quad 2-Input Exclusive-OR Gate  
Features  
General Description  
High Speed: t = 4.8ns (typ.) at V = 5V  
The VHC86 is an advanced high speed CMOS Quad  
Exclusive OR Gate fabricated with silicon gate CMOS  
technology. It achieves the high speed operation similar  
to equivalent Bipolar Schottky TTL while maintaining the  
CMOS low power dissipation.  
PD  
CC  
Low Power Dissipation: I = 2µA (max.) @ T = 25°C  
CC  
A
High Noise Immunity: V  
= V  
= 28% V (min.)  
NIH  
NIL CC  
Power down protection is provided on all inputs  
Low Noise: V = 0.8V (max.)  
OLP  
An input protection circuit ensures that 0V to 7V can be  
applied to the input pins without regard to the supply  
voltage. This device can be used to interface 5V to 3V  
systems and on two supply systems such as battery  
back up. This circuit prevents device destruction due to  
mismatched supply and input voltages.  
Pin and Function Compatible with 74HC86  
Ordering Information  
Package  
Order Number  
Number  
Package Description  
74VHC86M  
M14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"  
Narrow  
74VHC86SJ  
M14D  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74VHC86MTC  
MTC14  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,  
4.4mm Wide  
74VHC86N  
N14A  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.  
All packages are lead free per JEDEC: J-STD-020B standard.  
©1992 Fairchild Semiconductor Corporation  
74VHC86 Rev. 1.4.0  
www.fairchildsemi.com  

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