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74VHC595 PDF预览

74VHC595

更新时间: 2024-11-29 22:56:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 移位寄存器
页数 文件大小 规格书
9页 86K
描述
8-Bit Shift Register with Output Latches

74VHC595 数据手册

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August 1993  
Revised April 1999  
74VHC595  
8-Bit Shift Register with Output Latches  
An input protection circuit insures that 0V to 7V can be  
applied to the input pins without regard to the supply volt-  
age. This device can be used to interface 5V to 3V systems  
and two supply systems such as battery backup. This cir-  
cuit prevents device destruction due to mismatched supply  
and input voltages.  
General Description  
The VHC595 is an advanced high-speed CMOS Shift Reg-  
ister fabricated with silicon gate CMOS technology. It  
achieves the high-speed operation similar to equivalent  
Bipolar Schottky TTL while maintaining the CMOS low  
power dissipation.  
This device contains an 8-bit serial-in, parallel-out shift reg-  
ister that feeds an 8-bit D-type storage register. The stor-  
age register has eight 3-STATE outputs. Separate clocks  
are provided for both the shift register and the storage reg-  
ister. The shift register has a direct-overriding clear, serial  
input, and serial output (standard) pins for cascading. Both  
the shift register and storage register use positive-edge  
triggered clocks. If both clocks are connected together, the  
shift register state will always be one clock pulse ahead of  
the storage register.  
Features  
High Speed: tPD = 5.4 ns (typ) at VCC = 5V  
Low power dissipation: ICC = 4 µA (max) at TA = 25°C  
High noise immunity: VNIH = VNIL = 28% VCC (min)  
Power down protection is provided on all inputs  
Low noise: VOLP = 0.9V (typ)  
Pin and function compatible with 74HC595  
Ordering Code:  
Order Number Package Number  
Package Description  
74VHC595M  
74VHC595SJ  
74VHC595MTC  
74VHC595N  
M16A  
M16D  
MTC16  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
© 1999 Fairchild Semiconductor Corporation  
DS011640.prf  
www.fairchildsemi.com  

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