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74VHC574

更新时间: 2024-11-08 22:56:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器输出元件
页数 文件大小 规格书
10页 78K
描述
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING

74VHC574 数据手册

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74VHC574  
OCTAL D-TYPE FLIP FLOP  
WITH 3 STATE OUTPUT NON INVERTING  
HIGH SPEED:  
fMAX =180MHz(TYP.) at VCC =5V  
LOW POWER DISSIPATION:  
ICC =4 µA (MAX.) at TA =25 oC  
HIGH NOISEIMMUNITY:  
M
T
(Micro Package)  
(TSSOPPackage)  
VNIH = VNIL =28% VCC (MIN.)  
POWERDOWN PROTECTIONON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 8 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 2V to 5.5V  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES574  
ORDER CODES :  
74VHC574M  
74VHC574T  
at the D inputs.  
While the OE input is low, the 8 outputs will be in  
a normal logic state (high or low logic level) and,  
while high level, the outputs will be in a high  
impedance state.  
The output control does not affect the internal  
operation of flip flop; that is, the old data can be  
retained or the new data can be entered even  
while the outputs are off.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface5V to 3V.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
IMPROVED LATCH-UP IMMUNITY  
LOWNOISEVOLP = 0.9V(Max.)  
DESCRIPTION  
The 74VHC574 is an advanced high-speed  
CMOS OCTAL D-TYPE FLIP FLOP with 3  
STATE OUTPUT NON INVERTING fabricated  
with sub-micron silicon gate and double-layer  
metal wiring C2MOS technology.  
This 8 bit D-Type flip-flop is controlled by a clock  
input (CK) and an output enable input (OE).  
On the positive transition of the clock, the Q  
outputs will be set to logic states that were setup  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/10  
June 1999  

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