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74VHC374SJ PDF预览

74VHC374SJ

更新时间: 2024-11-08 22:56:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 逻辑集成电路光电二极管驱动
页数 文件大小 规格书
7页 95K
描述
Octal D-Type Flip-Flop with 3-STATE Outputs

74VHC374SJ 数据手册

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November 1992  
Revised April 1999  
74VHC374  
Octal D-Type Flip-Flop with 3-STATE Outputs  
and two supply systems such as battery back up. This cir-  
cuit prevents device destruction due to mismatched supply  
and input voltages.  
General Description  
The VHC374 is an advanced high speed CMOS octal flip-  
flop with 3-STATE output fabricated with silicon gate CMOS  
technology. It achieves the high speed operation similar to  
equivalent Bipolar Schottky TTL while maintaining the  
CMOS low power dissipation. This 8-bit D-type flip-flop is  
controlled by a clock input (CP) and an output enable input  
(OE). When the OE input is HIGH, the eight outputs are in  
a HIGH impedance state.  
Features  
High Speed: tPD = 5.4 ns (typ) at VCC = 5V  
High noise immunity: VNIH = VNIL = 28% VCC (Min)  
Power down protection is provided on all inputs  
Low power dissipation: ICC = 4 µA (Max) @ TA = 25°C  
An input protection circuit ensures that 0V to 7V can be  
applied to the input pins without regard to the supply volt-  
age. This device can be used to interface 5V to 3V systems  
Pin and function compatible with 74HC374  
Ordering Code:  
Order Number Package Number  
Package Description  
74VHC374M  
74VHC374SJ  
74VHC374MTC  
74VHC374N  
M20B  
M20D  
MTC20  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
D0–D7  
CP  
Description  
Data Inputs  
Clock Pulse Input  
OE  
3-STATE Output Enable Input  
3-STATE Outputs  
O0–O7  
© 1999 Fairchild Semiconductor Corporation  
DS011538.prf  
www.fairchildsemi.com  

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