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74VHC373T PDF预览

74VHC373T

更新时间: 2024-11-05 22:56:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
10页 78K
描述
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

74VHC373T 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP-20
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.1
Is Samacsys:N系列:AHC/VHC
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:6.5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.008 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源:5 V
Prop。Delay @ Nom-Sup:10.5 ns传播延迟(tpd):16.5 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
Base Number Matches:1

74VHC373T 数据手册

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74VHC373  
OCTAL D-TYPE LATCH  
WITH 3 STATE OUTPUT NON INVERTING  
HIGH SPEED:tPD =5.0ns (TYP.) atVCC = 5V  
LOW POWER DISSIPATION:  
ICC =4 µA (MAX.) at TA =25 oC  
HIGH NOISEIMMUNITY:  
M
T
VNIH = VNIL =28% VCC (MIN.)  
POWERDOWN PROTECTIONON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 8 mA (MIN)  
(Micro Package)  
(TSSOPPackage)  
ORDER CODES :  
74VHC373M  
74VHC373T  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
OPERATING VOLTAGERANGE:  
While the LE input is held at a high level, the Q  
outputswill follow the data inputs precisely. When  
the LE is taken low, the Q outputs will be latched  
precisely at the logic level of D input data. While  
the (OE) input is low, the 8 outputs will be in a  
normal logic state (high or low logic level) and  
while high level the outputs will be in a high  
impedance state.  
VCC (OPR)= 2V to 5.5V  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES373  
IMPROVED LATCH-UP IMMUNITY  
LOWNOISE:VOLP = 0.9V(Max.)  
DESCRIPTION  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface5V to 3V.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
The 74VHC373 is an advanced high-speed  
CMOS OCTAL D-TYPE LATCH with 3 STATE  
OUTPUT NON INVERTING fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C2MOS technology.  
This 8 bit D-Type latch is controlled by a latch  
enable input (LE) and an output enable input  
(OE).  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/10  
June 1999  

74VHC373T 替代型号

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