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74VHC373MTC PDF预览

74VHC373MTC

更新时间: 2024-11-04 22:56:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器锁存器逻辑集成电路光电二极管PC
页数 文件大小 规格书
8页 107K
描述
Octal D-Type Latch with 3-STATE Outputs

74VHC373MTC 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.07
Samacsys Confidence:4Samacsys Status:Released
Samacsys PartID:438146Samacsys Pin Count:20
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Small Outline Packages
Samacsys Footprint Name:MTC20 (MO-153)Samacsys Released Date:2017-12-16 07:28:40
Is Samacsys:N系列:AHC/VHC
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:6.5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.008 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:RAIL峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/5.5 VProp。Delay @ Nom-Sup:10.5 ns
传播延迟(tpd):16.5 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

74VHC373MTC 数据手册

 浏览型号74VHC373MTC的Datasheet PDF文件第2页浏览型号74VHC373MTC的Datasheet PDF文件第3页浏览型号74VHC373MTC的Datasheet PDF文件第4页浏览型号74VHC373MTC的Datasheet PDF文件第5页浏览型号74VHC373MTC的Datasheet PDF文件第6页浏览型号74VHC373MTC的Datasheet PDF文件第7页 
February 1993  
Revised April 2005  
74VHC373  
Octal D-Type Latch with 3-STATE Outputs  
General Description  
Features  
The VHC373 is an advanced high speed CMOS octal D-  
type latch with 3-STATE output fabricated with silicon gate  
CMOS technology. It achieves the high speed operation  
similar to equivalent Bipolar Schottky TTL while maintain-  
ing the CMOS low power dissipation. This 8-bit D-type  
latch is controlled by a latch enable input (LE) and an out-  
put enable input (OE). The latches appear transparent to  
data when latch enable (LE) is HIGH. When LE is LOW, the  
data that meets the setup time is LATCHED. When the OE  
input is HIGH, the eight outputs are in a high impedance  
state.  
High Speed: tPD 5.0 ns (typ) @ VCC 5V  
High Noise Immunity: VNIH VNIL 28% VCC (Min)  
Power Down Protection is provided on all inputs  
Low Noise: VOLP 0.6V (typ)  
Low Power Dissipation: ICC  
4 A (Max) @ TA 25 C  
Pin and Function Compatible with 74HC373  
An input protection circuit ensures that 0V to 7V can be  
applied to the input pins without regard to the supply volt-  
age. This device can be used to interface 5V to 3V systems  
and two supply systems such as battery back up. This cir-  
cuit prevents device destruction due to mismatched supply  
and input voltages.  
Ordering Code:  
Order Number Package Number  
Package Description  
74VHC373M  
74VHC373SJ  
74VHC373MTC  
74VHC373N  
M20B  
M20D  
MTC20  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
© 2005 Fairchild Semiconductor Corporation  
DS011555  
www.fairchildsemi.com  

74VHC373MTC 替代型号

型号 品牌 替代类型 描述 数据表
74VHC373MTC ONSEMI

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带 3 态输出的八路 D 型锁存
74VHC373MTCX ONSEMI

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带 3 态输出的八路 D 型锁存

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