February 1993
Revised April 2005
74VHC373
Octal D-Type Latch with 3-STATE Outputs
General Description
Features
The VHC373 is an advanced high speed CMOS octal D-
type latch with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintain-
ing the CMOS low power dissipation. This 8-bit D-type
latch is controlled by a latch enable input (LE) and an out-
put enable input (OE). The latches appear transparent to
data when latch enable (LE) is HIGH. When LE is LOW, the
data that meets the setup time is LATCHED. When the OE
input is HIGH, the eight outputs are in a high impedance
state.
■ High Speed: tPD 5.0 ns (typ) @ VCC 5V
■ High Noise Immunity: VNIH VNIL 28% VCC (Min)
■ Power Down Protection is provided on all inputs
■ Low Noise: VOLP 0.6V (typ)
■ Low Power Dissipation: ICC
4 A (Max) @ TA 25 C
■ Pin and Function Compatible with 74HC373
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Ordering Code:
Order Number Package Number
Package Description
74VHC373M
74VHC373SJ
74VHC373MTC
74VHC373N
M20B
M20D
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
Connection Diagram
IEEE/IEC
© 2005 Fairchild Semiconductor Corporation
DS011555
www.fairchildsemi.com