April 2007
74VHC373
tm
Octal D-Type Latch with 3-STATE Outputs
Features
General Description
■ High Speed: t = 5.0ns (typ) @ V = 5V
The VHC373 is an advanced high speed CMOS octal
D-type latch with 3-STATE output fabricated with silicon
gate CMOS technology. It achieves the high speed oper-
ation similar to equivalent Bipolar Schottky TTL while
maintaining the CMOS low power dissipation. This 8-bit
D-type latch is controlled by a latch enable input (LE)
and an output enable input (OE). The latches appear
transparent to data when latch enable (LE) is HIGH.
When LE is LOW, the data that meets the setup time is
LATCHED. When the OE input is HIGH, the eight
outputs are in a high impedance state.
PD
CC
■ High Noise Immunity: V
= V
= 28% V (Min.)
NIH
NIL
CC
■ Power Down Protection is provided on all inputs
■ Low Noise: V = 0.6V (Typ.)
OLP
■ Low Power Dissipation: I = 4µA (Max) @ T = 25°C
CC
A
■ Pin and Function Compatible with 74HC373
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
systems and two supply systems such as battery back
up. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Ordering Information
Package
Order Number
74VHC373M
Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC373SJ
74VHC373MTC
M20D
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the
ordering number. Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Descriptions
Pin Names
Description
D –D
Data Inputs
0
7
LE
Latch Enable Input
Output Enable Input
3-STATE Outputs
OE
O –O
0
7
©1993 Fairchild Semiconductor Corporation
74VHC373 Rev. 1.3
www.fairchildsemi.com