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74VHC373_04 PDF预览

74VHC373_04

更新时间: 2024-11-05 04:48:03
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输出元件
页数 文件大小 规格书
14页 310K
描述
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING

74VHC373_04 数据手册

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74VHC373  
OCTAL D-TYPE LATCH  
WITH 3 STATE OUTPUTS NON INVERTING  
HIGH SPEED: t = 5.0 ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 4 µA (MAX.) at T =25°C  
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
V
NIH  
NIL  
CC  
POWER DOWN PROTECTION ON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
SOP  
TSSOP  
|I | = I = 8 mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
Table 1: Order Codes  
PACKAGE  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 5.5V  
T & R  
V
CC  
SOP  
74VHC373MTR  
74VHC373TTR  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 373  
TSSOP  
IMPROVED LATCH-UP IMMUNITY  
LOW NOISE: V  
= 0.9V (MAX.)  
precisely at the logic level of D input data. While  
the (OE) input is low, the 8 outputs will be in a  
normal logic state (high or low logic level) and  
while (OE) is in high level, the outputs will be in a  
high impedance state.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface 5V to 3V.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
OLP  
DESCRIPTION  
The 74VHC373 is an advanced high-speed  
CMOS OCTAL D-TYPE LATCH with 3 STATE  
OUTPUTS NON INVERTING fabricated with  
sub-micron silicon gate and double-layer metal  
2
wiring C MOS technology.  
These 8 bit D-Type latch are controlled by a latch  
enable input (LE) and an output enable input (OE).  
While the LE inputs is held at a high level, the Q  
outputs will follow the data input precisely. When  
the LE is taken low, the Q outputs will be latched  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 4  
1/14  
November 2004  

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