November 1992
Revised February 2005
74VHC32
Quad 2-Input OR Gate
General Description
Features
The VHC32 is an advanced high speed CMOS 2-Input OR
Gate fabricated with silicon gate CMOS technology. It
achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
■ High Speed:
tPD 3.8 ns (typ) at VCC 5V
■ Low Power Dissipation:
ICC
2 A (Max) at TA 25 C
The internal circuit is composed of 4 stages including buffer
output, which provide high noise immunity and stable out-
put. An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
■ High Noise Immunity: VNIH VNIL 28% VCC (Min)
■ Power down protection is provided on all inputs
■ Low Noise: VOLP 0.8V (Max)
■ Pin and Function Compatible with 74HC32
Ordering Code:
Package
Order Number
Package Description
Number
74VHC32M
M14A
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC32MX_NL
(Note 1)
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC32SJ
M14D
MTC14
MTC14
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC32MTC
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC32MTCX_NL
(Note 1)
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74VHC32N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Symbol
Connection Diagram
IEEE/IEC
Truth Table
A
H
L
B
H
H
L
O
H
H
H
L
Pin Descriptions
Pin Names
Description
Inputs
Outputs
H
L
An, Bn
On
L
© 2005 Fairchild Semiconductor Corporation
DS011518
www.fairchildsemi.com