Datasheet > 74VHC32FT

74VHC32FT

更新时间： 2024-11-25 14:56:19

品牌	Logo	应用领域
东芝 - TOSHIBA		/
页数	文件大小	规格书
7页	153K
描述
Quad 2-Input/OR, TSSOP14B

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74VHC32FT 数据手册

74VHC32FT

CMOS Digital Integrated Circuits Silicon Monolithic

74VHC32FT

1. Functional Description

•

Quad 2-Input OR Gate

2. General

The 74VHC32FT is an advanced high speed CMOS 2-INPUT OR GATE fabricated with silicon gate C2MOS

technology.

It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS

low power dissipation.

The internal circuit is composed of 4 stages including buffer output, which provide high noise immunity and

stable output.

An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply

voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up.

This circuit prevents device destruction due to mismatched supply and input voltages.

3. Features

(1) AEC-Q100 (Rev. H) (Note 1)

(2) Wide operating temperature range: Topr = -40 to 125 

(3) High speed: tpd = 3.8 ns (typ.) at VCC = 5.0 V

(4) Low power dissipation: ICC = 2.0 µA (max) at Ta = 25 

(5) High noise immunity: VNIH = VNIL = 28 % VCC (min)

(6) Power down protection is provided on all inputs.

(7) Balanced propagation delays: tPLH ≈ tPHL

(8) Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V

(9) Low noise: VOLP = 0.8 V (max)

(10) Pin and function compatible with the 74 series (AC/HC/AHC/LV etc.) 32 type.

Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales

representative.

4. Packaging

TSSOP14B

Start of commercial production

2013-05

2017-02-22

Rev.4.0

12 3 4 5 6 7

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