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74VHC27N PDF预览

74VHC27N

更新时间: 2024-11-26 22:56:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 79K
描述
Triple 3-Input NOR Gate

74VHC27N 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.57
Is Samacsys:N系列:AHC/VHC
JESD-30 代码:R-PDIP-T14长度:19.18 mm
负载电容(CL):50 pF逻辑集成电路类型:NOR GATE
最大I(ol):0.008 A功能数量:3
输入次数:3端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/5.5 VProp。Delay @ Nom-Sup:9 ns
传播延迟(tpd):14 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:5.08 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

74VHC27N 数据手册

 浏览型号74VHC27N的Datasheet PDF文件第2页浏览型号74VHC27N的Datasheet PDF文件第3页浏览型号74VHC27N的Datasheet PDF文件第4页浏览型号74VHC27N的Datasheet PDF文件第5页浏览型号74VHC27N的Datasheet PDF文件第6页 
July 1994  
Revised April 1999  
74VHC27  
Triple 3-Input NOR Gate  
cuit prevents device destruction due to mismatched supply  
and input voltages.  
General Description  
The VHC27 is an advanced high speed CMOS 3-Input  
NOR Gate fabricated with silicon gate CMOS technology. It  
achieves the high-speed operation similar to equivalent  
Bipolar Schottky TTL while maintaining the CMOS low  
power dissipation.  
Features  
High speed: tPD = 4.1 ns (typ) at TA = 25°C  
Low power dissipation: ICC = 2 µA (max) at TA = 25°C  
High noise immunity: VNIH = VNIL = 28% VCC (min)  
The internal circuit is composed of 3 stages including buffer  
output, which provide high noise immunity and stable out-  
put. An input protection circuit insures that 0V to 7V can be  
applied to the input pins without regard to the supply volt-  
age. This device can be used to interface 5V to 3V systems  
and two supply systems such as battery backup. This cir-  
Power down protection is provided on all inputs  
Low noise: VOLP = 0.8V (max)  
Pin and function compatible with 74HC27  
Ordering Code:  
Order Number Package Number  
Package Description  
74VHC27M  
74VHC27SJ  
74VHC27MTC  
74VHC27N  
M14A  
M14D  
MTC14  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Truth Table  
Pin Descriptions  
A
H
X
X
L
B
X
H
X
L
C
X
X
H
L
Y
L
Pin Names  
An, Bn, Cn  
Yn  
Description  
Inputs  
Outputs  
L
L
H
X = Don't Care  
© 1999 Fairchild Semiconductor Corporation  
DS011682.prf  
www.fairchildsemi.com  

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