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74VHC273MSCX PDF预览

74VHC273MSCX

更新时间: 2024-01-25 11:34:09
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
7页 94K
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74VHC273MSCX 数据手册

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April 1994  
Revised April 1999  
74VHC273  
Octal D-Type Flip-Flop  
age. This device can be used to interface 5V to 3V systems  
and two supply systems such as battery backup. This cir-  
cuit prevents device destruction due to mismatched supply  
and input voltages.  
General Description  
The VHC273 is an advanced high speed CMOS Octal D-  
type flip-flop fabricated with silicon gate CMOS technology.  
It achieves the high speed operation similar to equivalent  
Bipolar Schottky TTL while maintaining the CMOS low  
power dissipation.  
Features  
High Speed: fMAX= 165 MHz (typ) at VCC = 5V  
Low power dissipation: ICC = 4 µA (max) at TA = 25°C  
High noise immunity: VNIH = VNIL = 28% VCC (min)  
The register has a common buffered Clock (CP) which is  
fully edge-triggered. The state of each D input, one setup  
time before the LOW-to-HIGH clock transition, is trans-  
ferred to the corresponding flip-flop’s Q output. The Master  
Reset (MR) input will clear all flip-flops simultaneously. All  
outputs will be forced LOW independently of Clock or Data  
inputs by a LOW voltage level on the MR input.  
Power down protection is provided on all inputs  
Low noise: VOLP = 0.9V (max)  
Pin and function compatible with 74HC273  
An input protection circuit insures that 0V to 7V can be  
applied to the inputs pins without regard to the supply volt-  
Ordering Code:  
Order Number Package Number  
Package Description  
74VHC273M  
74VHC273SJ  
74VHC273MTC  
74VHC273N  
M20B  
M20D  
MTC20  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
Description  
D0–D7  
Data Inputs  
Master Reset  
MR  
CP  
Clock Pulse Input  
Data Outputs  
Q0–Q7  
© 1999 Fairchild Semiconductor Corporation  
DS011670.prf  
www.fairchildsemi.com  

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