Datasheet > 74VHC245_04

74VHC245_04

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		总线收发器
页数	文件大小	规格书
12页	311K
描述
OCTAL BUS TRANSCEIVER (3-STATE)

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74VHC245_04 数据手册

74VHC245

OCTAL BUS

TRANSCEIVER (3-STATE)

■

HIGH SPEED: t = 4.0 ns (TYP.) at V = 5V

PD CC

LOW POWER DISSIPATION:

= 4 µA (MAX.) at T =25°C

■

HIGH NOISE IMMUNITY:

= V = 28% V (MIN.)

POWER DOWN PROTECTION ON

CONTROL INPUTS

NIH

NIL

SOP

TSSOP

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 8 mA (MIN)

Table 1: Order Codes

PACKAGE

BALANCED PROPAGATION DELAYS:

PLH

PHL

T & R

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 5.5V

SOP

74VHC245MTR

74VHC245TTR

TSSOP

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 245

■

IMPROVED LATCH-UP IMMUNITY

direction of data transmission is determined by

DIR input. The enable input G can be used to

disable the device so that the busses are

effectively isolated.

LOW NOISE: V

= 0.9V (MAX.)

OLP

DESCRIPTION

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

All floating bus terminals during High Z State must

be held HIGH or LOW.

The 74VHC245 is an advanced high-speed

CMOS OCTAL BUS TRANSCEIVER (3-STATE)

fabricated with sub-micron silicon gate and

double-layer metal wiring C MOS technology.

This IC is intended for two-way asynchronous

communication between data busses; the

Figure 1: Pin Connection And IEC Logic Symbols

Rev. 6

1/12

November 2004

12 3 4 5 6 7...12

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