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74VHC244SJX PDF预览

74VHC244SJX

更新时间: 2024-09-15 23:24:35
品牌 Logo 应用领域
其他 - ETC 驱动器
页数 文件大小 规格书
7页 88K
描述
Dual 4-Bit Non-Inverting Buffer/Driver

74VHC244SJX 数据手册

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November 1992  
Revised April 1999  
74VHC244  
Octal Buffer/Line Driver with 3-STATE Outputs  
cuit prevents device destruction due to mismatched supply  
and input voltages.  
General Description  
The VHC244 is an advanced high speed CMOS octal bus  
buffer fabricated with silicon gate CMOS technology. It  
achieves high speed operation similar to equivalent Bipolar  
Schottky TTL while maintaining the CMOS low power dissi-  
pation. The VHC244 is a non-inverting 3-STATE buffer hav-  
ing two active-LOW output enables. These devices are  
designed to be used as 3-STATE memory address drivers,  
clock drivers, and bus oriented transmitter/receivers.  
Features  
High Speed: tPD = 3.9ns (typ) at VCC = 5V  
High noise immunity: VNIH = VNIL = 28% VCC (min)  
Power down protection is provided on all inputs  
Low noise: VOLP = 0.6V (typ)  
An input protection circuit ensures that 0V to 7V can be  
applied to the input pins without regard to the supply volt-  
age. This device can be used to interface 5V to 3V systems  
and two supply systems such as battery back up. This cir-  
Low power dissipation: ICC = 4 µA (max) @ TA = 25°C  
Pin and function compatible with 74HC244  
Ordering Code:  
Order Number Package Number  
Package Description  
74VHC244M  
74VHC244SJ  
74VHC244MTC  
74VHC244N  
M20B  
M20D  
MTC20  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
OE1, OE2  
Description  
3-STATE Output Enable Inputs  
Inputs  
I0–I7  
O0–O7  
3-STATE Outputs  
© 1999 Fairchild Semiconductor Corporation  
DS011522.prf  
www.fairchildsemi.com  

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